Package Substrate Skip Vias for Uniform Signal Transmission
Solution Overview
Problem
Existing package substrates face challenges in achieving uniform signal transmission speeds between electronic components due to variations in signal line widths and thicknesses, leading to potential processing delays and inefficiencies.
Innovation Solution
A package substrate design featuring a dedicated wiring layer sandwiched by resin insulating layers, with specific via conductors and pad configurations that maintain precise insulation distances and conductor layer thicknesses, ensuring consistent signal transmission speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional wiring layers with varying widths and thicknesses are used to connect electronic components, then the substrate can accommodate multiple components, but signal transmission speeds become non-uniform leading to processing delays
Solution Approach 1:
The patent applies parameter changes by precisely controlling the insulation distances (t1 and t2) between conductor layers and maintaining their difference within 5 μm. This parameter control ensures uniform signal transmission characteristics across different wiring paths, eliminating processing delays caused by variable transmission speeds.
Solution Approach 2:
The patent introduces skip via conductors as intermediary elements that penetrate through both the outermost and inner resin insulating interlayers to directly connect the outermost and second conductor layers. These intermediary via conductors provide dedicated signal paths that maintain uniform transmission characteristics by bypassing intermediate wiring layers with potentially varying parameters.
2Productivity
If insulation distance between conductor layers is reduced to increase wiring density, then more components can be mounted, but signal integrity and insulation reliability may deteriorate
Solution Approach 1:
The patent optimizes the insulation distance parameters (t1 and t2) to achieve a balance between wiring density and insulation reliability. By specifying that the sum of t1 and t2 is 40 μm or less while maintaining their difference within 5 μm, the design achieves high wiring density without compromising signal integrity or insulation performance.
Solution Approach 2:
The patent transitions from planar wiring to three-dimensional multi-layer wiring with controlled via conductors. By utilizing the vertical dimension with skip via conductors penetrating through multiple insulating layers, the design achieves high wiring density while maintaining reliable insulation distances through precise vertical positioning and control of layer thicknesses.
Data Source
AI summary
A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.