Semiconductor package device and method of manufacturing the same
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Solution Overview
Problem
Conventional interposer-based 2.5D packaging technologies are inefficient, costly, and difficult to adapt to design changes, limiting productivity and performance improvements in semiconductor packaging.
Innovation Solution
A semiconductor package device comprising a circuit substrate unit with vertical conductive via elements and horizontal conductive pattern layers, a molding layer, and a redistribution layer, allowing for the integration of heterogeneous chips with improved electrical connectivity and ease of design modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interposer-based 2.5D packaging is used, then chip interconnection is achieved, but productivity is low and production cost is high
Solution Approach 1:
The packaging substrate is divided into a carrier substrate and a package substrate that can be separately manufactured and then integrated. The package substrate is further segmented into multiple unit package areas, allowing parallel processing and assembly, which significantly improves productivity and manufacturing efficiency
Solution Approach 2:
The patent transitions from conventional planar interconnection to three-dimensional vertical interconnection through conductive via elements extending through the package substrate. This vertical dimension enables higher density interconnection and improves manufacturing efficiency by allowing simultaneous processing of multiple layers
2Adaptability or versatility
If conventional interposer technology is used, then chip interconnection is achieved, but adaptability to design changes is poor
Solution Approach 1:
The package substrate design allows for flexible configuration of conductive via elements and unit package areas, enabling easy adaptation to different chip interconnection requirements. The modular structure permits reconfiguration for various design changes without requiring complete redesign of the interposer
Solution Approach 2:
The package substrate serves multiple functions: it provides mechanical support, electrical interconnection through conductive vias, and flexible chip mounting surfaces. This multi-functional design enhances adaptability to different packaging configurations while reducing overall device complexity
3Reliability
If through silicon via or through mold via is used for electrical connection, then chip interconnection is achieved, but ball pitch increases
Solution Approach 1:
The patent uses vertical conductive via elements extending through the package substrate to achieve three-dimensional interconnection. This vertical routing allows electrical connections without increasing the horizontal ball pitch, maintaining compact packaging while ensuring reliable electrical connection between chips
Data Source
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AI summary
Disclosed are a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes a circuit substrate unit including a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction, a molding layer configured to form a single substrate shape along with the circuit substrate unit while filling the space around the circuit substrate unit, the molding layer being disposed so as to expose the circuit substrate unit, a redistribution layer member disposed on a first surface of a package substrate including the circuit substrate unit and the molding layer, and a plurality of chips mounted on the redistribution layer member so as to be electrically connected to the redistribution layer member.