Electronic Package Substrate Layout to Prevent Warpage
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Solution Overview
Problem
Conventional semiconductor packages experience warpage due to uneven stress distribution caused by coefficient of thermal expansion mismatches, leading to separation and breakage of solder bumps and electrical disconnections, which reduces product yield.
Innovation Solution
A substrate structure with a routing layer featuring linear conductive traces in the die placement area and sheet-shaped circuits in the functional area, where the linear traces have a narrower width than the sheet-shaped circuits, dispersing stress and preventing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sheet-shaped circuit with wider width is used to connect passive elements and semiconductor chips, then electrical connection reliability is improved, but stress concentration increases causing warpage and solder bump separation
Solution Approach 1:
The patent segments the circuit pattern into two distinct types: linear conductive traces for connecting to the semiconductor chip and sheet-shaped circuits for connecting to passive elements. This segmentation allows each circuit type to be optimized for its specific function, with linear traces minimizing stress at the chip interface and sheet-shaped circuits providing adequate electrical connection for passive elements.
Solution Approach 2:
The patent applies different circuit geometries to different regions of the substrate. In the die placement area, linear conductive traces with narrower width are used to minimize stress concentration. In the functional area, sheet-shaped circuits with wider width are used to ensure adequate electrical connection for passive elements. This local differentiation resolves the contradiction between electrical reliability and stress management.
2Length of moving object
If the substrate thickness is reduced to meet thinning requirements, then device miniaturization is achieved, but structural stability decreases leading to increased warpage
Solution Approach 1:
The circuit layer is segmented into linear traces and sheet-shaped circuits with different geometries. The linear traces in the die placement area are specifically designed to minimize stress concentration, which helps maintain structural stability even when the substrate is thinned to meet miniaturization requirements.
3Ease of manufacture
If uniform circuit patterns are used across the entire substrate, then manufacturing simplicity is maintained, but stress distribution becomes uneven causing warpage
Solution Approach 1:
The patent implements local quality by using different circuit patterns in different regions: linear conductive traces in the die placement area and sheet-shaped circuits in the functional area. This regional differentiation optimizes stress distribution while remaining compatible with standard PCB manufacturing processes, thus balancing manufacturing simplicity with stress management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces stress concentration, preventing warpage and bump separation, enhancing electrical connection reliability and production yield while meeting thinning requirements.
Implementation Method 1
the package substrate 10 is prone to uneven stress distribution due to differences (e.g., mismatches) in Coefficient of Thermal Expansion (CTE) in various regions of the surface
Data Source
AI summary
An electronic package is provided, which includes a substrate structure and an electronic element and a passive element disposed on the substrate structure, where a die placement area and a functional area separated from each other are defined on a surface of a substrate body of the substrate structure, so that a routing layer is arranged with linear conductive traces with a smaller width in the die placement area, and a sheet-shaped circuit with a larger width and electrically connected to the linear conductive traces is arranged in the functional area, so as to reduce a metal area on the surface of the substrate body, thereby avoiding the problem of warpage caused by stress concentration in the die placement area.