Semiconductor Package Substrate Structure for Stress and Warpage Reduction
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Solution Overview
Problem
Conventional methods of manufacturing semiconductor package substrates are complicated and lack precision, particularly in forming through-holes and patterning copper foils, leading to low manufacturing efficiency and increased complexity.
Innovation Solution
A semiconductor package substrate design incorporating a base substrate with stress reducing portions, such as slots and trenches, filled with resin to enhance manufacturing precision and reduce warpage, utilizing a conductive material with plating layers on both surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional method of forming through-holes and patterning copper foils is used, then the manufacturing process can be completed, but the manufacturing process becomes complicated and precision is low
Solution Approach 1:
The invention extracts and eliminates the complex through-hole formation and copper foil patterning steps from the manufacturing process. By using a pre-formed conductive base substrate with integrated conductive patterns, the patent removes the need for conventional drilling, plating, and photoresist patterning operations, thereby simplifying the manufacturing process while improving precision
Solution Approach 2:
The conductive base substrate is prepared in advance with pre-formed conductive patterns and through-holes already established. This preliminary preparation eliminates the need for complex in-process patterning operations, allowing the manufacturing process to proceed more simply and with higher precision
2Manufacturing precision
If stress reducing portions are added to the base substrate, then warpage is reduced and manufacturing precision is enhanced, but the structural complexity increases
Solution Approach 1:
The stress reducing portions are strategically placed only in specific locations on the base substrate where stress accumulation occurs. Rather than modifying the entire substrate structure, the invention applies stress relief features locally at critical areas, thereby reducing warpage and improving manufacturing precision without significantly increasing overall structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves manufacturing efficiency by reducing stress and warpage, ensuring precise electrical connections and enhanced structural integrity of the semiconductor package substrate.
Implementation Method 1
the base substrate includes a stress reducing portion configured to reduce stress
Implementation Method 2
a first plating layer disposed on a top surface of the base substrate, and a second plating layer disposed on the bottom surface of the base substrate
Data Source
AI summary
A semiconductor package substrate includes a base substrate including a conductive material and having a first groove or first trench located in a bottom surface of the base substrate, a resin filled into the first groove or first trench, a first plating layer disposed on a top surface of the base substrate, and a second plating layer disposed on the bottom surface of the base substrate, wherein the base substrate includes a stress reducing portion configured to reduce stress.