Packaged Die and RDL Bonding Structure for Warpage Control

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Solution Overview

Problem

The semiconductor industry faces challenges in miniaturization, higher speed, greater bandwidth, and lower power consumption due to the need for smaller and more creative packaging techniques as process nodes shrink below 20 nm, where existing packaging methods struggle with warpage and thermal expansion mismatches during the formation of redistribution layers.

Innovation Solution

A 3D integrated fan-out package-on-package (PoP) device is formed using a die package with a redistribution layer on a carrier substrate, where the redistribution layer is bonded to the die package, reducing warpage and thermal expansion issues by using a rigid carrier substrate with a similar coefficient of thermal expansion, and employing bonding structures like micro bumps or solder balls for electrical and physical coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing packaging methods are used for sub-20 nm process nodes, then manufacturing simplicity is maintained, but warpage and thermal expansion mismatches occur during redistribution layer formation

Engineering Contradiction:
Improvewarpage controlVSAvoidpackaging technique complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The packaging structure is divided into multiple segments: a first substrate, a second substrate, and a redistribution layer formed on the second substrate. The redistribution layer is separated from the first substrate by removing a portion of the second substrate, creating distinct functional regions that can be optimized independently for thermal expansion control and electrical connection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The redistribution layer acts as an intermediary between the first substrate and the external environment. It is formed on the second substrate and provides electrical connections while the rigid carrier substrate serves as a mediator to control thermal expansion and prevent warpage during the packaging process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If process node is shrunk below 20 nm for higher integration density, then miniaturization and higher speed are achieved, but packaging techniques become more difficult and warpage increases

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar packaging to three-dimensional packaging by forming a redistribution layer on a second substrate and selectively removing portions of the second substrate. This creates vertical connections and allows for higher integration density while maintaining manufacturing precision through the rigid carrier substrate support.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If redistribution layer is formed on a flexible substrate, then ease of manufacture is improved, but warpage control deteriorates

Engineering Contradiction:
Improveredistribution layer formationVSAvoidsubstrate stability
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The packaging structure uses a composite material system consisting of a first substrate, a second substrate, and a redistribution layer. The rigid carrier substrate provides dimensional stability and controls thermal expansion, while the redistribution layer provides electrical connectivity, combining the advantages of both rigid and flexible materials.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient miniaturization, reduces warpage, and minimizes thermal expansion mismatches, allowing for smaller, faster, and lower power semiconductor packages with improved integration density and reduced latency.

Implementation Method 1

employing bonding structures like micro bumps or solder balls for electrical and physical coupling

Methodology Applied
Scientific EffectSoldering: Soldering

Implementation Method 2

reducing warpage and thermal expansion issues by using a rigid carrier substrate with a similar coefficient of thermal expansion

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11996401B2Packaged die and RDL with bonding structures therebetween
Publication Date: 2024.05.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11996401B2 patent drawing
  • US11996401B2 patent drawing
  • US11996401B2 patent drawing

AI summary

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.