Advanced Packaging Interconnect Structure Without Lithography
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Solution Overview
Problem
The existing methods for advanced semiconductor packaging, such as wafer-level packaging, are costly and time-consuming due to the use of physical vapor deposition, photolithography, and etching processes, which are labor-intensive and require expensive equipment.
Innovation Solution
A method for forming an interconnect structure that involves screen printing a passivation layer, electroless plating to form a wiring layer and metal layer, and electroless plating to create a second pad, eliminating the need for deposition, photolithography, and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical vapor deposition, photolithography and etching processes are used for fabricating interconnect structures, then manufacturing precision and reliability are improved, but process cost and time increase significantly
Solution Approach 1:
The patent extracts and eliminates the complex PVD, photolithography and etching processes from the interconnect fabrication workflow. Instead, it uses a simplified approach with screen printing to deposit conductive paste and electroplating to form metal layers, thereby removing unnecessary process steps while maintaining functional requirements.
Solution Approach 2:
The patent replaces expensive, hermetic equipment required for PVD and photolithography with simpler, more accessible equipment for screen printing and electroplating. This substitution uses less sophisticated, more cost-effective tools that can be operated in non-hermetic environments, reducing both equipment cost and operational complexity.
2Manufacturing precision
If physical vapor deposition, photolithography and etching processes are used for fabricating interconnect structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex multi-step process sequence of PVD, photolithography and etching, replacing it with a simpler two-step process of screen printing followed by electroplating. This extraction of unnecessary complexity maintains the essential functionality while reducing process burden.
Solution Approach 2:
Instead of following the conventional top-down approach of depositing precise patterns through PVD and photolithography, the patent inverts the methodology by using screen printing to create a conductive paste pattern first, then using electroplating to build up metal layers conformally over this pattern, achieving the desired interconnect structure through reversed process sequencing.
3Manufacturing precision
If physical vapor deposition, photolithography and etching processes are used for fabricating interconnect structures, then manufacturing precision is improved, but equipment cost increases
Solution Approach 1:
The patent substitutes expensive, specialized equipment for PVD and photolithography with inexpensive, readily available equipment for screen printing and electroplating. This replacement dramatically reduces capital investment and operational costs while eliminating the requirement for hermetic processing environments.
Solution Approach 2:
The patent replaces the complex mechanical and vacuum-based systems of PVD and photolithography with simpler wet chemical processes. Screen printing uses basic mechanical deposition, and electroplating uses aqueous chemistry, both of which can be performed in ambient conditions without sophisticated vacuum chambers or photolithography tools.
4Reliability
If conventional processes are used for interconnect fabrication, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent implements continuous processing where screen printing deposits conductive paste that is immediately followed by electroplating in a sequential, uninterrupted manner. This continuous workflow eliminates idle time between steps and enables higher throughput compared to the discrete, batch-oriented conventional processes.
Solution Approach 2:
The patent uses simple, non-hermetic processing equipment that can operate continuously in ambient conditions, replacing the expensive, hermetic equipment that requires complex environmental control and cannot operate continuously. This enables sustained high-speed production without the bottlenecks of environment-controlled processing chambers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces process time and equipment costs, enhancing production efficiency and productivity by simplifying the interconnect fabrication process.
Implementation Method 1
forming a metal layer on a surface of the wiring layer by electroless plating, thereby forming an interconnect
Implementation Method 2
forming a wiring layer on a surface of the first passivation layer by screen printing
Implementation Method 3
forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole
Data Source
AI summary
An interconnect structure for advanced packaging and method for the interconnect structure are disclosed. The method includes: providing a semiconductor substrate to be packaged having surface on which there is a first pad having conduction-promoting surface; depositing a first passivation layer on surface of the semiconductor substrate, the first pad is exposed from first passivation layer, forming a wiring layer on surface of the first passivation layer by screen printing, and forming a metal layer on surface of the wiring layer by electroless plating, wherein the wiring layer covers the first pad; forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein there is a through hole in the second passivation layer, in which the metal layer is exposed; and forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole.