Semiconductor Packaging Structure With Stress Relief for Warpage

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Solution Overview

Problem

The semiconductor industry faces challenges with warpage issues due to coefficient of thermal expansion (CTE) mismatch between carrier substrates and molding materials in integrated fan-out (InFO) packages, leading to reduced yield and reliability of semiconductor devices.

Innovation Solution

Incorporation of a stress relief layer with a low coefficient of thermal expansion (CTE) to reduce the effective CTE of the packaging structure, minimizing warpage and enhancing the tolerance of semiconductor dies by using materials like SiOx, SiOCN, or SiOxNy, which are deposited conformally to surround components and reduce film stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a die is embedded in molding material with a carrier substrate in InFO package technology, then integration density is improved, but warpage occurs due to CTE mismatch between carrier substrate and molding material

Engineering Contradiction:

Improveintegration densityVSAvoidwarpage

Core Design Contradiction:

Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

A stress relief layer is introduced as an intermediary component between the carrier substrate and the molding material. This layer has a low coefficient of thermal expansion (CTE) that acts as a buffer to compensate for the CTE mismatch between the carrier substrate and molding material, thereby reducing warpage while maintaining the InFO package structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the thermal expansion parameter by selecting materials with specific CTE properties for the stress relief layer. The layer's low CTE is specifically chosen to counterbalance the high CTE of the molding material, creating a compensated system that maintains dimensional stability during thermal processing

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If carrier substrate and molding material are bonded together, then package structure is formed, but CTE mismatch causes warpage and reduces yield

Engineering Contradiction:

Improvepackage structure formationVSAvoidyield

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The stress relief layer serves as a mediator between the carrier substrate and molding material, allowing them to be bonded together while compensating for their incompatible thermal expansion properties. This maintains ease of manufacture while improving reliability by reducing warpage-induced defects

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses a composite structure consisting of the carrier substrate, stress relief layer, and molding material. The composite design allows each layer to contribute its specific properties, with the stress relief layer's low CTE compensating for the molding material's high CTE, thereby maintaining structural integrity and improving yield

Inventive Principle:

Principle #40Composite materials

3Adaptability or versatility

If redistribution structure is formed on die over carrier substrate, then functionality is enhanced, but warpage increases due to material CTE mismatch

Engineering Contradiction:

ImprovefunctionalityVSAvoidwarpage

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The stress relief layer acts as a stable foundation that supports the formation of the redistribution structure. By reducing warpage at the base level, it enables the redistribution structure to be formed with better planarity and reduced stress, maintaining functionality while improving stability

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress relief layer effectively reduces warpage, increasing the process window and joint yield of semiconductor devices by maintaining structural integrity during manufacturing processes, thereby improving the reliability and performance of semiconductor packages.

Implementation Method 1

Warpage of the carrier substrate and the materials disposed thereon can occur as a result of coefficient of thermal expansion (CTE) mismatch between the carrier substrate and the molding material

Methodology Applied

Scientific EffectCoefficient of thermal expansion (CTE): Thermal Expansion

Implementation Method 2

The stress relief layer effectively reduces warpage, increasing the process window and joint yield of semiconductor devices by maintaining structural integrity during manufacturing processes

Methodology Applied

Scientific EffectFilm stress: Stress Relaxation

Data Source

PatentUS20260033341A1Packaging structure and methods of forming the same

Publication Date: 2026.01.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A packaging structure and methods of forming the same are described. In some embodiments, the structure includes a through via, a first semiconductor die disposed adjacent the through via, a stress relief layer disposed on side surfaces of the through via and side surfaces of the first semiconductor die, and a molding material disposed on the stress relief layer and between the through via and the first semiconductor die. Top surfaces of the through via, the semiconductor die, and the molding material are substantially coplanar.