Packaging Substrate Intermediate Insulating Layer Wiring
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in increasing wiring density due to obstacles in circuit layers, leading to increased circuit area and design complexity, particularly when dealing with regions that require circuit extensions or interlayer vias.
Innovation Solution
A method for manufacturing a packaging substrate involves machining an intermediate insulating layer and wiring layer to cover obstacle regions, allowing for local staggered-layer wiring and a thinner build-up structure, thereby improving wiring density without the need for interlayer vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connecting circuits are extended to avoid obstacle regions in the same circuit layer, then the obstacle region is avoided, but the circuit wiring area and wiring difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar wiring to three-dimensional staggered-layer wiring. By utilizing intermediate insulating layers between circuit layers, connecting circuits can be routed through multiple dimensions, avoiding obstacles without extending wiring area. The intermediate insulating layer provides an additional spatial dimension for circuit routing, enabling connections to pass over or under obstacle regions vertically rather than horizontally.
2Reliability
If connecting circuits are arranged in adjacent circuit layers with interlayer vias, then the obstacle region is avoided, but the packaging substrate becomes thicker and design difficulty increases
Solution Approach 1:
The patent applies local quality by selectively placing intermediate insulating layers only where needed to bridge specific circuit layers, rather than uniformly increasing the substrate structure throughout. The intermediate insulating layer is localized to specific regions where staggered-layer wiring is required, allowing the substrate to maintain its original thickness in areas without such wiring needs.
3Reliability
If interlayer vias are machined to connect circuits across layers, then circuit connections are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the connection function from traditional interlayer vias by using intermediate insulating layers with conductive patterns that provide alternative connection paths. Instead of relying on vertical vias to penetrate through multiple layers, the design separates the connection function into lateral wiring on intermediate layers, eliminating the need for complex via machining operations.
Data Source
AI summary
A method for manufacturing a packaging substrate, and a packaging substrate are disclosed. The method includes: providing a bottom board with a first circuit layer, the first circuit layer being provided with at least one demand point, and one side of the demand point being provided with a first to-be-avoided region; machining a first intermediate insulating layer on the bottom board, the first intermediate insulating layer including a first intermediate insulating dielectric covering the first to-be-avoided region; machining a first intermediate wiring layer on the first intermediate insulating layer, the first intermediate wiring layer including a first intermediate circuit partially arranged on the first intermediate insulating dielectric and connected to the demand point; machining a first insulating layer on the first intermediate wiring layer which is stacked on the bottom board and covers the first intermediate wiring layer; and machining a circuit build-up layer on the first insulating layer.