Processor with Packed Instruction Converter for Parallel Execution
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Solution Overview
Problem
Existing digital signal processors face challenges in improving processing performance for large amounts of data, as they require significant time and resources due to serial data processing, and methods like SIMD and VLIW trade off between instruction memory size and execution efficiency.
Innovation Solution
A processor design that includes an instruction memory, a converter to unpack packed instructions into multiple codes, and multiple operation units for parallel execution, allowing for increased instructions per cycle while reducing instruction memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the instruction code length is reduced to decrease instruction memory size, then the instruction memory capacity is reduced, but the number of cycles required to execute multiple instructions increases
Solution Approach 1:
The instruction execution process is segmented into multiple parallel paths. The instruction memory is divided into multiple banks (first instruction memory and second instruction memory) that can be accessed simultaneously. Instructions are fetched from different memory banks in parallel and executed by different operation units, allowing multiple instructions to be processed concurrently without increasing the capacity of each individual memory bank.
Solution Approach 2:
The patent transitions from sequential single-instruction execution to multi-dimensional parallel execution. By introducing multiple instruction memory banks and multiple operation units, the system executes instructions along multiple dimensions simultaneously (different instruction streams for different data sets), effectively increasing throughput without expanding the fundamental instruction storage capacity.
2Productivity
If multiple instruction slots are provided to increase instructions executed per cycle, then the execution efficiency is improved, but the instruction code length and instruction memory size increase
Solution Approach 1:
Multiple operation units share common control resources including the instruction decoder and control logic. The decoder and control unit are designed to handle multiple instruction formats universally, allowing the same hardware to process different types of instructions across multiple parallel streams without requiring separate dedicated control logic for each instruction type.
Solution Approach 2:
The patent merges multiple instruction fetch operations into a unified parallel execution framework. Instructions from different memory banks are combined and fed to multiple operation units simultaneously. The control system merges the coordination of multiple instruction streams into a single control cycle, enabling efficient parallel execution without proportionally increasing control hardware.
Data Source
AI summary
A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in accordance with the decoding result of the instruction decoder. Therefore, the number of instructions that can be executed in parallel per cycle may be increased while at the same time the capacity of the instruction memory is reduced.