Packet Switch Logic Replication for Multi-Clock Domain Synchronization
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Solution Overview
Problem
Traditional data buffer methods for hardware-assisted design verification of integrated circuits with multiple clock domains are inefficient and require additional hardware and complex software for synchronization, often limited by memory bandwidth and physical constraints.
Innovation Solution
A packet switch-based system that compiles source and destination circuits with virtual channels to forward signal data from multiple clock domains into a single queue, allowing for efficient synchronization and emulation of the source logic with a delay, utilizing a single buffer to maximize memory bandwidth and eliminate the need for separate buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate FIFO buffers are used for each clock domain, then synchronization of signal data across multiple clock domains is achieved, but hardware complexity and memory requirements increase significantly
Solution Approach 1:
The patent merges multiple separate FIFO buffers into a single shared FIFO buffer that serves all clock domains. The packet switch routes packets from different clock domains through this single buffer, eliminating the need for multiple separate buffers while maintaining synchronization through virtual channel mapping and packet sequencing.
Solution Approach 2:
The single FIFO buffer is designed to handle packets from multiple clock domains simultaneously, making it a universal buffer that performs the function of multiple dedicated buffers. The packet switch enables this buffer to be accessed by different clock domains through virtual channel arbitration, achieving multi-functionality without requiring separate hardware for each domain.
2Productivity
If off-chip memory is used to increase buffering capacity, then memory bandwidth is improved, but board space and pin limitations are exceeded
Solution Approach 1:
The patent combines multiple clock domain buffers into a single shared buffer resource, maximizing the utilization of available on-chip memory space. By using a packet switch to manage access from multiple clock domains, the system achieves high buffering capacity without requiring additional off-chip memory, thus avoiding board space and pin limitations.
3Quantity of substance
If multiple FIFOs are built from a single physical memory, then memory resource utilization is improved, but bandwidth limitations and context switching overhead increase
Solution Approach 1:
The packet switch acts as an intermediary between multiple clock domains and the single physical memory buffer. It manages memory access requests from different clock domains, arbitrates bandwidth allocation, and prevents context switching overhead by maintaining dedicated virtual channels that map directly to memory address spaces, thus maximizing memory bandwidth utilization.
4Reliability
If traditional data buffer methods are used, then hardware-assisted verification is enabled, but additional hardware and complex software are required
Solution Approach 1:
The packet switch enables the buffer system to self-manage synchronization across clock domains without requiring complex external software control. The virtual channel mapping, packet routing, and buffer management are handled automatically by the packet switch hardware, eliminating the need for complex software synchronization mechanisms while maintaining verification capability.
Data Source
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AI summary
A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels. The destination logic may emulate the source logic synchronized with the plurality of clock domains delayed by the delay period.