Pad Structure for High Speed Nonvolatile Memory
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face slow response speeds due to increased resistance and capacitance resulting from the distance between peripheral circuits and pads, which hinders their integration and performance.
Innovation Solution
A nonvolatile memory device design featuring a 3D memory array with a 'Cell Over Peri' structure, where the peripheral circuit is disposed below the memory cell array, and a pad is positioned on the first metal layer, reducing the distance between the pad and the peripheral circuit, thereby minimizing resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between peripheral circuit and pad is increased to accommodate 3D structure, then integration density is improved, but response speed deteriorates due to increased resistance and capacitance
Solution Approach 1:
The patent transitions from a planar 2D layout to a three-dimensional stacked architecture where memory cell arrays are arranged vertically above peripheral circuits. Multiple metal layers (first metal layer, second metal layer, third metal layer) are stacked at different heights, creating vertical interconnections that reduce the horizontal distance between pads and peripheral circuits while maintaining high integration density.
Solution Approach 2:
The patent implements a nested structure where the first metal layer with cell region interconnections is positioned within the vertical space above the peripheral circuit, and the second metal layer with peripheral region interconnections is positioned at a lower level. This nested arrangement allows signal paths to be routed through multiple hierarchical levels, reducing the effective distance between pads and peripheral circuits.
2Area of stationary object
If peripheral circuit is placed below memory cell array in Cell Over Peri structure, then area utilization is improved, but pad-to-peripheral-circuit distance increases causing higher resistance and capacitance
Solution Approach 1:
The patent divides the metal interconnection system into distinct segments: a first metal layer for cell region interconnections positioned above the peripheral circuit, a second metal layer for peripheral region interconnections positioned at a lower level, and a third metal layer for additional routing. This segmentation allows optimized signal paths where the pad on the first metal layer can connect to the peripheral circuit through vertical interconnections, reducing the effective distance despite the Cell Over Peri arrangement.
Solution Approach 2:
The patent introduces vertical interconnections (via holes, contact plugs) as intermediary elements that bridge the first metal layer containing the pad and the second metal layer containing peripheral region interconnections. These intermediaries provide direct vertical pathways through the stacked structure, minimizing the resistance and capacitance that would otherwise result from longer lateral routing paths.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.