Pad-less Pillar Interconnects for Finer Pitch IC Packaging
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Solution Overview
Problem
Current interconnect technologies face challenges in achieving finer pitches between first-level interconnect structures due to size constraints and alignment limitations, leading to defects such as bridging, as dies shrink in size and require more precise lithography processes.
Innovation Solution
The implementation of pad-less pillars that extend through electrically insulative material, allowing for direct contact with dies without intervening pads, and the use of laser drilling techniques to create tapered profiles, which increases alignment tolerance and reduces manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used to fabricate FLI structures, then manufacturing precision is maintained at current capabilities, but pitch between interconnect structures cannot be reduced further due to alignment limitations
Solution Approach 1:
The patent removes the intermediate pad structure from the conventional FLI architecture, extracting the problematic alignment-critical interface. By going directly from die contact to pillar interconnect without an intervening pad, the design eliminates the alignment tolerance accumulation that occurs at multiple interfaces, enabling finer pitch fabrication with current lithography capabilities
Solution Approach 2:
Instead of trying to improve lithography alignment precision to achieve finer pitch, the patent inverts the approach by simplifying the interconnect structure to reduce alignment sensitivity. The pad-less design inverts the conventional wisdom that pads are necessary for alignment, showing that removing them actually improves manufacturability at finer pitches
2Quantity of substance
If pitch between FLI structures is decreased to accommodate smaller dies, then die density is improved, but manufacturing defects such as bridging increase
Solution Approach 1:
By removing the pad structure entirely, the patent reduces the total width of the interconnect footprint. This extraction of the pad element allows pitch reduction without proportionally reducing the functional interconnect dimensions, maintaining reliability while increasing die density
Solution Approach 2:
The patent changes the geometric parameters of the interconnect structure by eliminating the pad, which alters the relationship between pitch and functional interconnect width. This parameter change enables higher density packaging while maintaining adequate spacing to prevent bridging defects
3Manufacturing precision
If conventional pad-based FLI structures are used, then alignment tolerance is limited by pad dimensions, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and removes the pad layer from the interconnect stack, simplifying the overall structure. This reduction in structural complexity decreases the number of fabrication steps and materials required, thereby reducing manufacturing cost while improving alignment tolerance through the direct die-contact-to-pillar interface
Solution Approach 2:
The patent inverts the conventional approach by demonstrating that removing alignment assistance features (pads) rather than adding more alignment features actually improves alignment tolerance. This inversion challenges the assumption that more structure equals better alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher density interconnects with improved alignment tolerance and reduced manufacturing costs, while maintaining or exceeding the required pitch and width specifications, thus enhancing the reliability and performance of integrated circuit package assemblies.
Implementation Method 1
the use of laser drilling techniques to create tapered profiles
Data Source
AI summary
Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed.