Page-Based Redundant Rows for Soft Post-Package Repair
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Solution Overview
Problem
Existing memory devices face challenges in efficiently repairing defective memory cells post-packaging, which can lead to performance delays and reduced yield, particularly due to the time-consuming nature of antifuse programming and the difficulty in accessing packaged devices for repair.
Innovation Solution
Implementing soft post-package repair (SPPR) using volatile memory to store defective address data, allowing for remapping of addresses to redundant rows or columns, and utilizing a controller to manage the repair process externally, enabling efficient and rapid recovery of defective memory cells without disrupting the operation of non-defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antifuse programming is used for post-package repair, then defective memory cells can be repaired, but the repair process takes approximately 200 milliseconds which impacts memory performance
Solution Approach 1:
The patent applies preliminary action by pre-configuring redundant rows and columns in the memory array during manufacturing. These redundant structures are prepared in advance and can be immediately activated when defects are detected, eliminating the need for time-consuming post-package repair processes. The row remapping circuit is pre-built to handle defect remapping without requiring external programming operations.
Solution Approach 2:
The patent extracts the repair function from the time-consuming antifuse programming process and integrates it into the memory array structure itself through dedicated redundant rows and columns. The repair capability is built into the hardware architecture rather than being applied as a separate post-processing step, thereby eliminating the 200ms delay associated with external antifuse programming.
2Reliability
If hardware modification using antifuses is performed, then address remapping to functional memory cells is achieved, but the complexity of the repair process increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to perform its own repair operations through an integrated row remapping circuit that automatically detects defective cells and redirects addresses to functional cells. The system uses built-in test modes and self-diagnostic capabilities to identify defects and activate redundant structures without requiring external programming equipment or complex manual intervention.
Solution Approach 2:
The patent applies universality by designing the redundant rows and columns to serve multiple purposes: they can be used for defect remapping, for testing during manufacturing, and for maintaining memory capacity under various failure conditions. The row remapping circuit handles both pre-package and post-package repair scenarios, making the repair mechanism universally applicable across different defect types and timing conditions.
3Reliability
If post-package repair is performed, then defective memory cells can be corrected, but access to the packaged device for repair becomes difficult
Solution Approach 1:
The patent applies preliminary action by completing all repair infrastructure setup during the manufacturing process. Redundant rows, columns, and the row remapping circuit are configured and tested before packaging, so that when defects are detected after packaging, the repair mechanisms are already in place and can be activated through simple control signals without requiring physical access or complex external programming equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability and yield of memory devices by allowing for rapid and efficient repair of defective cells post-packaging, reducing performance delays and waste of non-defective memory resources, while maintaining overall device functionality.
Implementation Method 1
An antifuse can have a structure similar to that of a capacitor, i.e., two conductive electrical terminals are separated by a dielectric layer. To create an electrically conductive path, a relatively high voltage is applied across the terminals, breaking down the interposed dielectric layer and forming a conductive link between the antifuse terminals.
Data Source
AI summary
Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.