Page Buffer Circuit Analog Bit Line Voltage Control
Solution Overview
Problem
The existing double verification method in nonvolatile memory devices lacks precise control over bit line voltages based on the program degree of memory cells, which hinders the narrowing of threshold voltage distributions during programming operations.
Innovation Solution
A page buffer circuit with a bit line control unit that temporarily charges and controls the voltage of selected bit lines in an analog manner according to the program state of memory cells, using charge and transfer control signals to adjust the voltage level, thereby enabling more accurate voltage control during double verification operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional double verification method is used, then the program operation can be performed, but the threshold voltage distribution cannot be effectively narrowed due to lack of precise bit line voltage control
Solution Approach 1:
The patent applies preliminary action by precharging the bit line to different voltage levels before the verification operation based on the program state. The bit line is precharged to a first voltage level for cells that have passed the first verification and to a second voltage level for cells that have failed, enabling differentiated control before the actual verification occurs.
Solution Approach 2:
The patent implements local quality by applying different voltage levels to the bit line based on local program states of memory cells. Specifically, different bit lines receive different precharge voltages (first voltage level vs. second voltage level) according to their individual program verification results, allowing precise local control of the verification process.
2Productivity
If the program speed is increased, then productivity improves, but the threshold voltage distribution widens reducing reliability
Solution Approach 1:
The patent applies dynamics by making the bit line voltage level dynamic and adjustable based on the program state. The system transitions from a static fixed voltage approach to a dynamic approach where the bit line voltage can be switched between different levels (first voltage level and second voltage level) depending on the program verification results, enabling adaptive control of program speed and threshold voltage distribution.
Solution Approach 2:
The patent implements parameter changes by varying the bit line voltage parameter according to the program state. The voltage level on the bit line is changed between a first voltage level and a second voltage level based on whether memory cells have passed or failed the first verification, allowing control over the program operation characteristics and threshold voltage distribution.
3Manufacturing precision
If precise voltage control is implemented through analog method, then threshold voltage distribution is narrowed, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the verification process into distinct stages (first verification and second verification) and by categorizing memory cells into different groups based on their program state (passed vs. failed). This segmentation allows the use of different voltage levels for different cell groups, achieving precise control without requiring complex continuous analog control circuits for all cells simultaneously.
Solution Approach 2:
The patent uses the bit line as an intermediary element to transfer and differentiate voltage levels to memory cells based on their program state. The page buffer circuit acts as an intermediary that receives program verification results and converts them into differentiated precharge voltage levels on the bit line, simplifying the control architecture compared to direct cell-by-cell control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise control of program speed and voltage distribution, effectively narrowing the threshold voltage distribution of memory cells by adjusting the bit line voltage based on the program state, ensuring reliable programming operations.
Implementation Method 1
A page buffer circuit with a bit line control unit that temporarily charges and controls the voltage of selected bit lines in an analog manner according to the program state of memory cells
Implementation Method 2
a page buffer circuit configured to control the program speed by checking the threshold voltage of a cell more accurately through a double verification operation using an analog method
Implementation Method 3
the program operation of a flash memory cell is mainly performed by applying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the semiconductor substrate
Data Source
AI summary
A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.