Page Buffer Cache Reuse for Continuous Memory Page Programming

Solution Overview

Problem

Existing memory devices face challenges in reducing data loading windows and circuit size due to the need for multiple latches in page buffers, which affect sequential program operations and memory cell density.

Innovation Solution

Implementing a multi-cache data loading scheme in page buffers that reuses latches for caching both current and next data pages, reducing the number of latches required and eliminating data loading windows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple latches are used in page buffers to store current and next data pages, then data loading window is reduced, but circuit size increases

Engineering Contradiction:

Improvedata loading windowVSAvoidcircuit size

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by enabling latches to serve dual purposes: storing both current data page information and next data page information. Specifically, latches in the page buffer circuit are configured to reuse their storage capacity across different data pages, allowing a single latch to function as both a current data storage unit and a next data cache unit, thereby reducing the total number of latches needed while maintaining continuous data loading capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements preliminary action by pre-caching next data page information in latches before the current data page programming operation is completed. This allows the next data page to be ready for immediate programming without waiting for the current page to finish, eliminating data loading windows and improving sequential program performance

Inventive Principle:

Principle #10Preliminary action

2Productivity

If multiple latches are used in page buffers to store current and next data pages, then sequential program performance is improved, but memory device size increases

Engineering Contradiction:

Improvesequential program performanceVSAvoidmemory device size

Core Design Contradiction:

ProductivityVSVolume of stationary object

Solution Approach 1:

The patent applies multi-functionality by enabling latches to serve dual purposes: storing both current data page information and next data page information. Specifically, latches in the page buffer circuit are configured to reuse their storage capacity across different data pages, allowing a single latch to function as both a current data storage unit and a next data cache unit, thereby reducing the total number of latches needed while maintaining continuous data loading capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements discarding and recovering by reusing latch storage capacity that becomes available after current data page programming is complete. The latches that were used for current data page storage are then recovered and reused for caching next data page information, maximizing the utilization of existing circuit resources without requiring additional dedicated storage elements

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS12555635B2Memory device having cache storage unit for storage of current and next data pages and program operation thereof

Publication Date: 2026.02.17 YANGTZE MEMORY TECH CO LTD

AI summary

A memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit configured to, in programming a select memory cell of the select row to one of 2N levels based on the current data page, store one of N bits of the current data page and one of N bits of a next data page in a time division manner.