Page Buffer Charge Sharing for Low-Voltage Flash Sensing Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in operating voltage of flash memory devices leads to a decrease in sensing node voltage range, making it difficult to maintain both on-cell and off-cell margins, thereby complicating the determination of memory cell states.
Innovation Solution
A charge sharing operation is performed between the SO node and the SOC node of the page buffer to lower the voltage level of the first node, enhancing the sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the operating voltage of the flash memory is lowered to reduce power consumption, then power consumption decreases, but the voltage range at the sensing node decreases making it difficult to correctly determine memory cell states
Solution Approach 1:
The sensing operation is divided into two separate sensing operations instead of one. The first sensing operation senses the voltage level of the sensing node, and the second sensing operation senses the voltage level after the charge sharing operation. This segmentation allows the system to maintain accurate sensing capability by capturing the state before and after the charge sharing event, thereby preserving measurement precision even at lower operating voltages.
Solution Approach 2:
A charge sharing operation is performed between the first node (sensing node) and the second node before the second sensing operation. This preliminary action of charge sharing modifies the voltage levels in a controlled manner, creating distinct voltage states that can be reliably detected. By preparing the voltage levels in advance through charge sharing, the system ensures sufficient sensing margin is available when the actual data sensing occurs.
2Use of energy by stationary object
If the operating voltage of the page buffer is decreased to match the lower flash memory voltage, then power consumption reduces, but the on-cell margin and off-cell margin cannot be secured simultaneously
Solution Approach 1:
The system dynamically adjusts the voltage levels at the sensing node through the charge sharing operation. By controlling the timing and execution of the charge sharing between the first and second nodes, the system creates dynamic voltage transitions that enhance the distinction between on-cell and off-cell states. This dynamic voltage adjustment maintains reliable sensing margins even when the overall operating voltage is reduced for lower power consumption.
Solution Approach 2:
The invention changes the voltage parameter at the sensing node by performing charge sharing between the first node and the second node. This parameter change creates a larger voltage swing or more distinct voltage levels, which improves the ability to reliably distinguish between different memory cell states. By modifying the voltage parameter dynamically through charge sharing, the system maintains sensing reliability despite operating at lower overall voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively secures both on-cell and off-cell margins, ensuring accurate determination of memory cell states even at low operating voltages.
Implementation Method 1
performs a charge sharing operation between the first node and the second node according to the sensing information of the first sensing operation during the second sensing operation
Data Source
AI summary
An example memory device comprises a memory cell array, a page buffer circuit, and a control logic circuit. The memory cell array comprises a plurality of memory cells each storing a plurality of data. The page buffer circuit comprises a plurality of page buffers connected to each memory cell through bit lines, and each page buffer comprises a first node that senses data stored in the memory cell and a second node connected to the first node through a transistor. The control logic circuit controls first and second sensing operations of the page buffer circuit by providing page buffer control signals to the page buffer circuit. Each page buffer stores sensing information of the first sensing operation in the first node and the second node, and performs a charge sharing operation between the first node and the second node according to the sensing information during the second sensing operation.