Page Buffer Circuit Parallel Sensing for 3D NAND Read Latency
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Solution Overview
Problem
Existing 3D NAND memory devices face challenges in scaling planar memory cells due to process technology limitations and reliability issues, leading to inefficiencies in read operations and increased latency.
Innovation Solution
The implementation of a page buffer circuit with multiple bit line segment sensing branches, each connected to a separate bit line segment and including a low-voltage latch or sense latch, allows for parallel pre-charge, develop, and sensing operations across multiple bit line segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller die sizes, then storage density increases, but process technology limitations and reliability issues worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional (3D) memory architecture with vertically stacked memory cells. This dimensional change allows continued increase in storage density without further shrinking lateral dimensions, thereby avoiding the process technology limitations and reliability degradation associated with aggressive planar scaling.
2Productivity
If multiple bit line segments are connected to separate page buffers, then read operations can be performed independently, but the number of page buffers and periphery circuit MOSs increases
Solution Approach 1:
The patent merges multiple bit line segment sensing operations into a single shared page buffer circuit. The page buffer is configured to simultaneously sense and process signals from multiple bit line segments (e.g., BL1A, BL1B, BL2A, BL2B) through shared sensing nodes and latch circuits, enabling parallel read operations without proportionally increasing the number of page buffers.
Solution Approach 2:
The page buffer circuit is designed with multi-functional capability to handle sensing operations for multiple bit line segments. The sensing branches and latch circuits can be selectively activated to serve different bit line segments based on operational requirements, allowing a single page buffer to perform the functions that would traditionally require multiple dedicated buffers.
3Loss of time
If traditional single bit line segment sensing is used, then page buffer circuit design is simple, but read latency increases
Solution Approach 1:
The patent segments the bit lines into multiple segments (e.g., BL1A/BL1B, BL2A/BL2B) that can be independently sensed and processed. Each bit line segment is connected to sensing branches within the page buffer, allowing parallel sensing operations to proceed simultaneously, thereby reducing overall read latency without requiring a complete redesign of the page buffer architecture.
Data Source
AI summary
A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.