Page Buffer Clock Branching for High-Speed Memory I/O
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Solution Overview
Problem
Existing memory devices face challenges in efficiently transmitting data at high speeds due to limitations in data transmission pathways, which hinder the ability to meet the increasing demands of modern electronic devices.
Innovation Solution
The memory device incorporates a peripheral circuit with parallel clock and data paths, including branch nodes and combined clock and data signals, to enhance data transmission efficiency by allowing simultaneous processing and transmission of data from multiple partitions, thereby increasing the data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel data transmission pathways are increased to meet high-speed data transmission demands, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The page buffer is divided into multiple partitions (first partition, second partition, third partition, fourth partition), each capable of independent data transmission. This segmentation allows parallel data pathways to operate simultaneously, increasing data transmission speed while managing complexity through modular organization of buffer components
Solution Approach 2:
The patent introduces multiple clock paths (first clock path, second clock path, third clock path) and corresponding data paths that operate in parallel dimensions. Branch nodes combine clock signals from multiple partitions and distribute them through different paths to the input/output node, creating multi-dimensional parallel transmission that increases speed without proportionally increasing complexity
2Productivity
If multiple clock paths are used to transmit combined clock signals, then parallelism is increased, but path length and signal routing complexity increase
Solution Approach 1:
Branch nodes are introduced to combine clock signals from multiple partitions (first partition and second partition feed first branch node; third partition and fourth partition feed second branch node). This merging approach allows parallel signal paths to converge at strategic points, increasing effective parallelism while managing path length through consolidation rather than allowing signals to traverse the entire device independently
Data Source
AI summary
The present disclosure provides memory devices and operation methods thereof, and memory systems. A peripheral circuit of an example memory device includes: a page buffer including a plurality of partitions, wherein each partition is configured to receive a clock signal and output a return clock signal based on the clock signal; a first branch node connected with two partitions of the plurality of partitions, and configured to combine the return clock signals outputted by the two partitions to generate a first combined clock signal; a first clock path with two ends respectively connected with the first branch node and an input/output node, and configured to transmit the first combined clock signal to the input/output node; a second branch node; and a second clock path.