Page Buffer With Shared Floating Node For Size Reduction
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Solution Overview
Problem
As electronic devices continue to shrink in size, there is a demand for smaller page buffer circuitry in memory devices, which existing latch circuits have not adequately addressed, particularly in terms of size reduction and performance improvement.
Innovation Solution
A page buffer design incorporating a static latch and a dynamic latch with a shared floating node, where data is stored in a storage capacitor through charge sharing based on capacitance ratios, allowing for reduced size and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If existing latch circuits are used for page buffer, then data storage function is provided, but the circuit size cannot be reduced sufficiently
Solution Approach 1:
The patent combines a static latch and a dynamic latch into a single integrated circuit structure. The static latch (comprising first and second static latches) and dynamic latch (comprising third and fourth dynamic latches) share common transistors and nodes, merging multiple latch functions into one compact unit while maintaining data storage reliability through the complementary nature of static and dynamic latch mechanisms.
Solution Approach 2:
The page buffer circuit is designed to perform multiple functions within a single structure: data latching, data storage, and data transfer operations. The same transistors and nodes serve multiple purposes - for example, the first transistor serves as both a latch element in the static latch and a control element for charge transfer, achieving multi-functionality that reduces overall circuit size.
2Area of stationary object
If latch circuit size is reduced, then area is saved, but performance may deteriorate
Solution Approach 1:
The latch circuit is segmented into distinct functional units - static latch portions for stable data holding and dynamic latch portions for fast data transfer. This segmentation allows each unit to be optimized for its specific function while working together, maintaining high performance despite reduced overall area. The first and second static latches handle stable storage while the third and fourth dynamic latches handle rapid data movement.
Solution Approach 2:
The circuit employs dynamic elements including the dynamic latch structure with storage capacitors and controlled charge transfer mechanisms. The fourth transistor acts as a dynamic switch that can rapidly transfer charge between nodes, enabling fast data retrieval operations. This dynamic behavior allows the compact circuit to achieve high-speed performance comparable to larger traditional latches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the formation of a page buffer with reduced size and enhanced performance, ultimately minimizing the size of the memory device while maintaining effective data storage and retrieval operations.
Implementation Method 1
storing data from the static latch to a storage capacitor of a dynamic latch through a floating node, wherein the data from the static latch is stored in the storage capacitor by charge sharing based on a ratio of capacitance of the floating node to capacitance of the storage capacitor
Data Source
AI summary
A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.