Page Buffer Grouping for Faster Memory Sensing Operations
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Solution Overview
Problem
The increasing demand for multi-functionalization and high integration of memory devices leads to complex wiring layouts and increased data transfer times, deteriorating data processing performance due to shared sensing nodes among input/output units.
Innovation Solution
A memory device with a page buffer circuit that classifies page buffers into groups, controlling operations such as precharge, discharge, and sensing periods differently for each group to optimize data processing efficiency, including separate arrangements of page buffer units and cache units, and using pass transistors to manage electrical connections among sensing nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple input/output units share a combined sensing node to increase integration degree, then device integration is improved, but data transfer time increases and data processing performance deteriorates
Solution Approach 1:
The patent divides the page buffers into multiple groups (first group and second group), with each group having its own dedicated sensing nodes. This segmentation eliminates the shared sensing node bottleneck, allowing parallel operations within each group and reducing data transfer time while maintaining high integration through the grouped structure.
2Adaptability or versatility
If page buffer size is reduced to increase integration degree, then device integration is improved, but wiring layout complexity increases
Solution Approach 1:
The patent merges page buffers within each group to share common sensing nodes and control logic, reducing individual page buffer sizes and simplifying wiring layouts. By combining resources at the group level while maintaining functional independence, the design achieves high integration without excessive wiring complexity.
3Measurement precision
If sensing operations are performed for all page buffers, then data accuracy is maintained, but data processing time increases
Solution Approach 1:
The patent segments page buffers into groups that can be operated independently. During verification operations, only the second group performs sensing operations while the first group performs precharge and discharge, halving the number of simultaneous sensing operations and doubling the effective processing throughput while maintaining data accuracy through subsequent verification.
Solution Approach 2:
The patent implements periodic sensing operations where different groups are activated at different times. The first group performs sensing during periods when the second group performs non-sensing operations, and vice versa. This time-division multiplexing maintains data accuracy through periodic verification while significantly improving overall data processing speed.
Data Source
AI summary
A memory device includes a memory cell array, a page buffer circuit including first to Nth page buffers, each page buffer including a sensing node, and a control logic configured to control page buffer operations, wherein the control logic is further configured to control the page buffer operations such that, in a first page buffer operation on a first page buffer included in a first group, a precharge period and a discharge period for a first sensing node of the first page buffer are performed, in a fifth page buffer operation on a fifth page buffer included in a second group, a precharge period and a discharge period for a fifth sensing node of the fifth page buffer are performed, and in a sensing period of the fifth page buffer operation, sensing operations on the first and fifth sensing nodes are performed together.