Page Buffer Latch Sampling for Nonvolatile Memory Read Accuracy
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Solution Overview
Problem
Nonvolatile memory devices face read failures due to widened threshold voltage distributions caused by charge leakage, program disturb, electrical coupling, temperature changes, and voltage changes, leading to inaccurate data reading and increased read time.
Innovation Solution
A nonvolatile memory device with a memory cell array and a page buffer circuit that includes multiple latches to sample voltages at different timings, determining memory cell states based on whether errors in read data are correctable, and outputting error-corrected data or data from subsequent latches when errors are uncorrectable, thereby improving read accuracy and reducing read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple latches are used to sample voltages at different timings, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The page buffer is divided into multiple latches (first latch, second latch, etc.), each responsible for sampling at different timings. This segmentation allows the system to capture voltage states at multiple critical moments during the read operation, improving accuracy without requiring a complete redesign of the buffer architecture.
Solution Approach 2:
The multiple latches are pre-configured to sample at predetermined timings during the read operation. By preparing these sampling points in advance, the system can efficiently capture threshold voltage distribution information at critical moments without adding complex real-time control logic.
2Measurement precision
If read retry is performed to handle read failures, then read accuracy is improved, but read time increases
Solution Approach 1:
The multiple latches perform preliminary sampling at different timings during the initial read operation, capturing voltage states that may indicate potential read failures. This preliminary action allows the system to identify and correct errors in the first read attempt, reducing or eliminating the need for time-consuming read retry operations.
Solution Approach 2:
The system uses the sampled voltage information from multiple latches as feedback to determine whether a read failure occurred and to select appropriate correction actions. This feedback mechanism enables real-time error detection and correction, allowing the system to handle read failures without always resorting to full read retry sequences.
3Reliability
If threshold voltage distributions are monitored to detect read failures, then read accuracy is improved, but measurement precision requirements increase
Solution Approach 1:
The threshold voltage distribution monitoring is segmented into multiple sampling events across different latches, each capturing voltage information at specific timings. This segmentation transforms a single high-precision measurement requirement into multiple lower-precision measurements taken at different moments, making the system more practical while maintaining reliable read failure detection.
Data Source
AI summary
A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≤N, L>1, P≤M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.