Page Buffer Circuit NBTI Compensation via Periodic Grounding
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Solution Overview
Problem
Non-volatile semiconductor memory devices face challenges in minimizing error bit generation and ensuring high reliability, particularly due to component degradation and negative bias temperature instability (NBTI) phenomena.
Innovation Solution
The implementation of a non-volatile memory device with a page buffer circuit that includes a memory cell, a bit line, a cross-coupled inverter for data storage, and transistors for ground voltage transmission. The control circuit operates the transistors during initialization and precharge periods to manage the sensing node and bit line, thereby reducing error bits and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sensing node is discharged and the bit line is precharged during initialization and precharge periods, then the data sensing capability is improved, but the threshold voltage shifts due to NBTI phenomenon causing error bits
Solution Approach 1:
The patent applies preliminary action by initializing the page buffer circuit before actual data sensing operations. The sensing node is discharged to ground and the bit line is precharged to a reference voltage level during an initialization period before the read operation begins. This preliminary preparation ensures that the circuit starts from a known state, improving measurement precision while the control circuit manages the timing to minimize NBTI effects
Solution Approach 2:
The patent implements periodic action by operating the first and second transistors in periodic cycles during initialization and precharge periods. The control circuit enables these transistors to transmit ground voltage to the cross-coupled inverter inputs at specific intervals, creating a periodic reset pattern that maintains reliability by preventing cumulative NBTI threshold voltage shifts while still achieving proper sensing initialization
2Measurement precision
If the page buffer circuit is initialized by discharging the sensing node and precharging the bit line, then the sensing accuracy is improved, but the operation time increases due to additional initialization and precharge periods
Solution Approach 1:
The patent merges the initialization and precharge operations into a unified sequence controlled by the control circuit. Both the sensing node discharge and bit line precharge are performed in an integrated manner during designated periods before the read operation, improving sensing accuracy while minimizing the total time required by combining these functions efficiently rather than executing them as separate sequential operations
Solution Approach 2:
The patent applies partial action by performing the initialization and precharge operations only for the minimum necessary duration required to achieve proper sensing accuracy. The control circuit enables the transistors for at least once during the initialization and precharge periods, which is sufficient to clear residual charges and establish proper voltage levels without unnecessarily extending the operation time beyond what is needed for accurate sensing
Data Source
AI summary
A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.