Page Buffer Layout Using Stacked Sensing Nodes for Read Reliability
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Solution Overview
Problem
The increasing integration and capacity demands of memory devices complicate the layout of wirings connected to semiconductor devices, particularly in page buffers, leading to reduced semiconductor device sizes and compromised reliability in read operations.
Innovation Solution
A page buffer circuit design with separated page buffer units and cache units, utilizing multiple metal layers for increased capacitance and shielding to reduce voltage variations, and a cell-over-periphery structure for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory device is increased, then capacity and integration are improved, but layout complexity of wirings increases
Solution Approach 1:
The page buffer is divided into separate page buffer units and cache units, with each unit having its own sensing nodes independently connected to bit lines. This segmentation allows for simplified wiring layout within each unit while achieving high overall integration through modular arrangement.
2Area of moving object
If semiconductor device size is decreased, then integration is improved, but reliability of read operations deteriorates
Solution Approach 1:
Multiple sensing nodes are connected to bit lines through different metal layers (first metal layer, second metal layer, third metal layer), utilizing vertical dimensionality to reduce voltage variations without increasing horizontal device footprint, thus maintaining small size while improving read reliability.
Solution Approach 2:
Multiple sensing nodes from different page buffer units are commonly connected to the same bit line through stacked metal layers, merging their functions to reduce voltage variations and improve read reliability while maintaining compact layout.
3Reliability
If multiple metal layers are used for sensing nodes, then voltage variations are reduced, but device complexity increases
Solution Approach 1:
The first, second, and third metal layers are used for multiple purposes: forming sensing nodes, providing shielding functions, and enabling common connections between multiple page buffer units. This multi-functionality reduces the need for additional dedicated structures, balancing reliability improvement with controlled complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the read reliability of memory devices by minimizing voltage variations and reducing layout complexity, while maintaining a compact size and high integration.
Implementation Method 1
utilizing multiple metal layers for increased capacitance
Implementation Method 2
utilizing multiple metal layers for increased capacitance and shielding to reduce voltage variations
Data Source
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AI summary
A memory device is described. The memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.