Page Buffer Circuit With Shared Sensing Nodes for Faster Data Dump
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Solution Overview
Problem
The increasing integration of memory devices necessitates a reduction in the size of the page buffer circuit while maintaining efficient data transfer operations.
Innovation Solution
A memory device with a page buffer circuit that includes a plurality of page buffer units connected through pass transistors, allowing parallel data dump operations between main latches and cache latches, and a structure that separates page buffer units from cache latches with a common coupling sensing node to reduce wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the page buffer circuit is integrated with cache latches in a traditional manner, then the circuit size is larger, but data transfer efficiency is lower
Solution Approach 1:
The patent merges the page buffer units and cache latches into a unified circuit structure where cache latches are integrated within the page buffer circuit. This integration allows data to be transferred directly between main latches and cache latches without external wiring, improving data transfer efficiency while optimizing the use of circuit area through shared resources and pathways.
Solution Approach 2:
The patent implements parallel data transfer pathways by enabling simultaneous data dump operations between multiple main latches and cache latches. This multi-dimensional approach to data transfer allows multiple data streams to flow concurrently through different pathways within the integrated circuit, significantly improving overall data transfer efficiency without proportionally increasing circuit area.
2Device complexity
If separate page buffer units and cache latches are used with individual wiring, then data transfer is simpler, but wiring complexity increases
Solution Approach 1:
The patent combines the wiring structures of page buffer units and cache latches into a unified internal connection system. By merging separate wiring pathways into integrated internal connections, the overall wiring complexity is reduced while maintaining straightforward data transfer operations through the unified structure.
3Speed
If parallel data dump operations are implemented, then data transfer speed increases, but circuit control complexity increases
Solution Approach 1:
The patent prepares control signals and circuit states in advance to enable parallel data dump operations. By pre-configuring the control logic and timing signals before parallel operations begin, the circuit can execute multiple data transfers simultaneously without requiring complex real-time control decisions, thus increasing data dump speed while keeping control complexity manageable.
Data Source
AI summary
A memory device includes a memory cell array including memory cells and a page buffer circuit including page buffer units respectively connected to the memory cells through a plurality of bit lines and cache latches respectively corresponding to the page buffer units, each of the page buffer units including a main latch and a pass transistor, each connected to a corresponding sensing node, sensing nodes of at least first, second, and third page buffer units of the page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.