Page Buffer Circuit Stepwise Discharge for Peak Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND type flash memory devices, the alternating program operations on even and odd bit lines result in voltage drops and peak currents due to sudden changes in bit line voltages, which are not effectively managed by existing technologies.
Innovation Solution
A page buffer circuit with a bit line selection unit, latch units, and a voltage control element that stepwise discharges precharged bit lines in response to program data states, using transistors and diodes or resistors to control voltage levels, thereby reducing voltage drops and peak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit line voltage is suddenly changed during alternating program operations on even and odd bit lines, then program operation speed is improved, but peak current increases and voltage drops occur
Solution Approach 1:
The bit line is precharged to a first voltage level before the program operation begins. This preliminary action prepares the bit line in advance, allowing the program operation to proceed at high speed while the voltage control element gradually discharges the bit line during the operation to prevent harmful peak currents and voltage drops.
Solution Approach 2:
The patent applies dynamic control of bit line voltage by using a voltage control element that gradually discharges the precharged bit line during the program operation. This dynamic adjustment allows the system to maintain high programming speed while continuously managing the voltage level to avoid peak current and voltage drop issues.
2Productivity
If bit line is precharged to high voltage level for fast programming, then programming speed is improved, but voltage drop and peak current occur during discharge
Solution Approach 1:
The bit line is precharged to a first voltage level before the program operation begins. This preliminary action prepares the bit line in advance, allowing the program operation to proceed at high speed while the voltage control element gradually discharges the bit line during the operation to prevent harmful peak currents and voltage drops.
Solution Approach 2:
The voltage control element monitors and controls the bit line voltage during the program operation, providing feedback control that ensures the voltage remains within acceptable ranges. This feedback mechanism maintains voltage stability while enabling high programming efficiency through controlled discharge.
3Quantity of substance
If alternating program operations are performed on even and odd bit lines, then data storage capacity is improved, but voltage drops and peak currents are generated
Solution Approach 1:
The patent divides the bit line discharge operation into segments by using a voltage control element that controls the discharge process in stages. This segmentation of the discharge operation allows alternating program operations on even and odd bit lines to proceed with high data storage capacity while managing voltage drops and peak currents through controlled, segmented discharge.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces peak currents by managing bit line voltage changes, ensuring stable operation and efficient data programming in nonvolatile memory devices.
Implementation Method 1
supplying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the semiconductor substrate
Implementation Method 2
using transistors and diodes or resistors to control voltage levels
Data Source
AI summary
A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a first voltage level, a first latch unit configured to store program data and output the stored program data to the sense node, a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state to a second voltage level, and a voltage control element configured to raise a voltage level of the sense node or drop a voltage level of the sense node to a third voltage level in response to a second control signal.