Page Buffer Bias Control for NAND Read Voltage Valley Search
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Solution Overview
Problem
Existing memory devices face challenges in accurately determining optimal read voltages due to overlapping distributions of threshold voltages in memory cells, leading to errors that conventional error correction circuits struggle to correct.
Innovation Solution
The memory device employs a valley search operation that controls bitlines to different bias states and applies sequential read voltages to selected wordlines, allowing for more efficient generation of cell count data to determine an optimal read voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read operations are used with standard bitline biasing, then the operation is simple and fast, but the read accuracy is insufficient due to overlapping threshold voltage distributions
Solution Approach 1:
The bitlines are divided into first bitlines and second bitlines with different bias states. The page buffer circuit selectively controls different bitline groups to be in different bias states during the valley search operation, enabling parallel acquisition of cell count data from multiple bitlines with different voltage conditions, thereby improving read accuracy without proportionally increasing complexity
Solution Approach 2:
The patent changes the bias state parameter of bitlines during the valley search operation. By adjusting bitline voltages to different bias states (e.g., different precharge voltages or sensing voltages), the system can differentiate between overlapping threshold voltage distributions and accurately determine the optimal read voltage, transforming a simple read operation into a more precise measurement process
2Measurement precision
If multiple read voltages are applied sequentially to determine optimal read voltage, then the accuracy improves, but the time required for the valley search operation increases
Solution Approach 1:
The valley search operation is segmented into parallel processes by dividing bitlines into different groups with different bias states. While multiple read voltages are applied sequentially to the selected wordline, multiple bitline groups simultaneously perform sensing operations with different bias conditions, allowing parallel data acquisition that reduces the overall time required for accurate optimal read voltage determination
Solution Approach 2:
The page buffer circuit maintains continuous sensing operations across different bitline groups during the valley search. By keeping bitlines in different bias states ready for sensing and continuously acquiring cell count data as each read voltage is applied, the system minimizes idle time and ensures that each voltage application phase productively contributes to determining the optimal read voltage
Data Source
AI summary
A memory device includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which a row decoder is connected to the plurality of memory cells through a plurality of wordlines, a plurality of page buffers connected to the plurality of memory cells through a plurality of bitlines, and a control logic controlling the row decoder and the plurality of page buffers are arranged. The row decoder inputs a plurality of read voltages having different levels to a selected wordline among the plurality of wordlines in sequence. Each of the plurality of page buffers includes a sensing node connected to one of the plurality of bitlines. Voltages of the sensing nodes included in the page buffers of a portion of the plurality of page buffers decrease differently while each of the plurality of read voltages is input to the selected wordline.