Page-Level Stripe Read Error Handling to Reduce Latency
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Solution Overview
Problem
Conventional DynamicXOR stripe-based read error handling in memory systems suffers from high latency and inefficient use of memory resources due to performing read error handling processes at the codeword level for each page, leading to repetitive and sequential execution for each failed codeword.
Innovation Solution
Implementing page-level stripe-based read error handling, where a stripe vector is generated using decoded and undecoded data from passing and failing codewords across multiple pages, reducing latency and memory usage by performing error correction at the page level rather than codeword level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read error handling is performed at the codeword level for each page, then error correction can be applied to individual failing codewords, but latency increases and memory resource usage becomes inefficient due to repetitive sequential execution
Solution Approach 1:
The patent merges multiple codeword-level error handling operations into a single page-level operation. When a page contains multiple failing codewords, the system performs error handling for the entire page at once rather than processing each failing codeword separately. This is achieved by generating a single stripe vector from all failing codewords in the page and using it to recover all failing codewords simultaneously, thereby reducing latency and eliminating repetitive sequential execution.
Solution Approach 2:
The patent segments the error handling process into two distinct phases: (1) generating a stripe vector from failing codewords and their corresponding parity information, and (2) using the stripe vector to recover all failing codewords. This segmentation allows the system to efficiently handle multiple failing codewords in parallel during the recovery phase, rather than processing them sequentially one at a time.
2Reliability
If read error handling is performed at the codeword level for each page, then individual error recovery is possible, but memory space requirements increase due to allocating buffers for each codeword operation
Solution Approach 1:
The patent combines the buffer requirements for multiple codeword operations into a single buffer allocation for the entire page. Instead of allocating separate buffers for each failing codeword's error handling operation, the system allocates one buffer to hold the stripe vector that serves all failing codewords in the page. This dramatically reduces the total memory buffer space required while maintaining the ability to recover all failing codewords accurately.
3Reliability
If conventional DynamicXOR stripe-based error handling is implemented, then error correction is provided for failing codewords, but the process becomes repetitive and sequential for each failed codeword, reducing productivity
Solution Approach 1:
The patent performs preliminary action by generating the stripe vector from all failing codewords and their parity information before the actual error recovery process. This pre-computed stripe vector is then reused for recovering all failing codewords in the page, eliminating the need to repeatedly compute parity information for each individual codeword. This preliminary preparation significantly accelerates the overall error recovery process while maintaining effective error correction.
Data Source
AI summary
Various embodiments provide for page-level and stripe-based read error handling for a memory system, such as a memory sub-system. For various embodiments, the page-level and stripe-based read error handling reduces the overall latency of a read error handling process (e.g., a multi-stage REH process). Additionally, various embodiments reduce the amount of memory space (e.g., buffer space) used during the stripe-based read error handling.