Panel-Level Multi-Die HPC Packaging With Glass-Reinforced Interconnects
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Solution Overview
Problem
High-performance computing (HPC) faces challenges in achieving zettascale performance due to limitations in wafer-level system integration, including size constraints and yield issues, which hinder the development of efficient packaging architectures that can meet the demands of applications requiring extreme computing power.
Innovation Solution
The implementation of panel-level components and systems using panel-level manufacturing techniques, which allow for the assembly of multiple integrated circuit dies on a single substrate with advanced interconnect structures, including glass reinforcement layers for mechanical stiffness and fine pitch geometries, enabling larger form factors and flexible integration of compute, I/O, memory, and thermal management components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level system integration is used, then manufacturing efficiency is improved, but size constraints and yield issues limit the ability to achieve zettascale performance
Solution Approach 1:
The patent segments the wafer-level integration approach into panel-level components, allowing multiple integrated circuit dies to be assembled on a single substrate in a modular fashion. This segmentation enables larger form factors while maintaining manufacturing efficiency by working with manageable panel-sized substrates rather than entire wafers.
Solution Approach 2:
The patent transitions from two-dimensional wafer-level integration to three-dimensional panel-level assembly, stacking multiple dies vertically on a single substrate. This dimensional change increases the effective packaging area and enables zettascale performance without proportionally increasing the substrate footprint.
2Area of stationary object
If panel-level manufacturing techniques are used to increase packaging area, then mechanical stability may be compromised without reinforcement structures
Solution Approach 1:
The patent employs composite material structures combining the substrate with reinforcement layers (such as glass or ceramic layers) to create a mechanically stable panel assembly. This composite approach allows large packaging areas to be achieved while maintaining sufficient mechanical strength through the synergistic combination of materials with complementary properties.
Solution Approach 2:
The patent applies reinforcement structures selectively at critical locations within the panel assembly rather than uniformly across the entire substrate. This local quality approach provides mechanical stability where needed while minimizing the impact on packaging area and maintaining cost-effectiveness.
3Reliability
If multiple integrated circuit dies are assembled on a single substrate, then design redundancy is improved, but interconnect complexity increases
Solution Approach 1:
The patent implements universal interconnect structures that can handle multiple functions: electrical connections, thermal management pathways, and mechanical support. This multi-functionality reduces the number of separate interconnect systems needed, thereby reducing overall complexity while supporting multiple dies for design redundancy.
Solution Approach 2:
The substrate acts as an intermediary component that simplifies the interconnection between multiple integrated circuit dies. By providing standardized connection interfaces and routing pathways on the substrate, the complexity of direct die-to-die interconnection is reduced, enabling easier assembly and maintenance of design redundancy.
Data Source
AI summary
Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.