Panel-Level Multi-Die HPC Packaging for Large-Area Interconnect Scaling
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Solution Overview
Problem
High-performance computing (HPC) faces challenges in achieving zettascale performance due to limitations in wafer-level system integration, including size constraints and yield issues, which hinder the development of efficient packaging architectures that can support increased interconnect density, bandwidth, and power efficiency.
Innovation Solution
The implementation of panel-level components and systems using panel-level manufacturing techniques, which allow for the assembly of integrated circuit dies and interconnections on a single substrate, enabling larger area designs and mechanical stiffness through glass reinforcement layers, and facilitating flexible thermal management and interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level system integration is used, then manufacturing efficiency is improved, but size constraints and yield issues limit the area and interconnect density
Solution Approach 1:
The patent divides the integration substrate into multiple panels that can be manufactured separately at wafer-level efficiency and then assembled together. Each panel contains a subset of the total interconnects and dies, allowing parallel manufacturing while achieving large-scale integration when panels are combined. This segmentation resolves the contradiction by maintaining manufacturing efficiency at the panel level while achieving large总面积 through assembly of multiple panels.
2Productivity
If wafer-level system integration is used, then manufacturing efficiency is improved, but yield issues arise due to large area defects
Solution Approach 1:
By segmenting the integration into multiple smaller panels manufactured separately, the patent reduces the defect probability in each panel while maintaining high manufacturing efficiency. Yield is improved because defects are confined to individual panels rather than affecting the entire large wafer, and defective panels can be replaced without reworking the entire system.
3Area of stationary object
If panel-level manufacturing is used to increase area, then interconnect density and bandwidth are improved, but device complexity increases
Solution Approach 1:
The patent manages complexity by segmenting the large integration area into standardized panels with repeating interconnect patterns and modular die arrangements. This modular approach allows complex large-area integration to be built from simpler, standardized panel units, reducing the overall complexity compared to designing a monolithic large-area structure.
Solution Approach 2:
The patent employs universal panel designs that can serve multiple functions and accommodate different die types and configurations. The standardized panel architecture with consistent interconnect patterns allows the same panel design to be reused across different applications and scaling requirements, reducing design complexity while achieving large integration areas.
4Power
If interconnect density is increased to achieve higher bandwidth, then power efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
By implementing high interconnect density within individual panels rather than across a single large wafer, the patent achieves high power efficiency while maintaining manufacturable precision levels. The segmentation allows standard fabrication processes to achieve the required precision within each panel without the compounding difficulties of manufacturing across a much larger area.
Solution Approach 2:
The patent optimizes interconnect parameters such as trace width, spacing, and length within each panel to achieve high density while remaining within the manufacturing capabilities of standard fabrication processes. By carefully controlling these parameters at the panel level, the system achieves high power efficiency without requiring beyond-state-of-the-art manufacturing precision.
Data Source
AI summary
Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.