Panel-Level Semiconductor Packaging With Wafer-Scale Interposer Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies face challenges in scaling beyond wafer dimensions due to limitations in fine-line/space resolution and thermal conductivity, particularly in high-end AI and HPC applications, where larger interposers and substrates are needed for enhanced performance and heat management.
Innovation Solution
A panel-level semiconductor package structure is developed, incorporating a panel-level substrate with an elastomeric connector and wafer-level package structures, featuring high-thermal-conductivity materials and advanced interconnects to enable efficient heat dissipation and high-density integration, utilizing larger rectangular panels for improved substrate utilization and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wafer-level processing techniques are used to fabricate interposers, then manufacturing precision and fine-line/space resolution can be maintained (minimum L/S about 2 μm/2 μm), but the area of the interposer is limited to wafer dimensions (maximum 300 mm×300 mm)
Solution Approach 1:
The patent segments the manufacturing process into two distinct levels: wafer-level processing for fabricating individual interposer units with high precision (2 μm/2 μm L/S), and panel-level assembly for combining multiple wafer-sized interposers into a large-scale panel structure. This segmentation allows each level to optimize for its specific function - precision fabrication at wafer-level and area expansion at panel-level - thereby resolving the contradiction between maintaining fine-line resolution and achieving large interposer area.
2Productivity
If panel-level processing is used to increase interposer area beyond wafer dimensions, then substrate utilization and throughput are improved, but fine-line/space resolution deteriorates (minimum L/S greater than 8 μm/8 μm in PCB substrate processing)
Solution Approach 1:
The patent segments the manufacturing process into two distinct levels: wafer-level processing for fabricating individual interposer units with high precision (2 μm/2 μm L/S), and panel-level assembly for combining multiple wafer-sized interposers into a large-scale panel structure. This segmentation allows each level to optimize for its specific function - precision fabrication at wafer-level and area expansion at panel-level - thereby resolving the contradiction between maintaining fine-line resolution and achieving large interposer area.
Solution Approach 2:
The patent introduces an intermediary carrier substrate that serves as a temporary platform for wafer-level interposer fabrication. This carrier substrate enables precise wafer-level processing while allowing the final panel structure to be assembled from multiple such units, thus bridging the gap between precision manufacturing constraints and large-scale area requirements.
3Productivity
If larger interposers are used to accommodate more GPUs and HBMs, then system performance is enhanced, but heat dissipation becomes more challenging due to increased thermal load
Solution Approach 1:
The patent segments the large thermal management problem into smaller, manageable units by creating a modular panel structure composed of multiple wafer-sized interposer units. Each unit can be independently thermally managed, and the distributed architecture allows heat to be spread across a larger total area, improving overall heat dissipation efficiency while maintaining high system performance.
Solution Approach 2:
The patent transitions from two-dimensional wafer-level thermal management to three-dimensional panel-level thermal management by stacking and arranging multiple interposer units in a panel configuration. This dimensional expansion provides additional thermal pathways and surface area for heat dissipation, enabling effective thermal management of high-performance GPU and HBM configurations.
Data Source
AI summary
A panel-level semiconductor package structure is provided. The panel-level semiconductor package structure includes a panel-level substrate structure and at least one wafer-level package structure. The panel-level substrate structure has a first side and a second side opposite to the first side. The wafer-level package structure is bonded over the panel-level substrate structure. Each of the wafer-level package structures includes a first redistribution layer (RDL) over the elastomeric connector and a plurality of first semiconductor devices laterally disposed over the first RDL. A method for manufacturing a panel-level substrate structure is also provided.