Panel-Level Wafer Reconstruction for Precise Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor packaging technologies require both panel-level and wafer-level equipment, leading to high costs and potential wafer cracking due to stress during encapsulation, while also being costly and inefficient in maintaining precision.
Innovation Solution
A panel-level packaging method that uses a hollowed plate to reconstruct wafers into panel-level form, allowing wafer-level packaging with panel-level equipment, reducing costs and avoiding wafer cracking by using a conductive structure and redistribution layers to maintain precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer-level packaging device is used to form redistribution structure, then processing precision is improved, but packaging cost increases
Solution Approach 1:
The patent merges the wafer-level redistribution function with panel-level packaging by forming the redistribution structure directly on the panel-level carrier board during the panel-level packaging process, eliminating the need for separate wafer-level equipment and reducing overall packaging cost while maintaining processing precision
Solution Approach 2:
The panel-level packaging device is designed to perform multiple functions: it serves as both the carrier for wafer mounting and the substrate for forming redistribution structures, enabling the same equipment to handle both positioning and electrical connection tasks that traditionally required separate specialized devices
2Adaptability or versatility
If wafer is cut into chips before mounting, then chip mounting flexibility is improved, but wafer stress and cracking risk increase
Solution Approach 1:
The redistribution structure is formed on the panel-level carrier board before the wafer is mounted and before the wafer is cut into chips. This preliminary formation of electrical connections allows the wafer to be cut into individual chips after mounting, providing mounting flexibility while avoiding the need to cut the wafer before mounting, thereby preventing wafer stress and cracking
Solution Approach 2:
The traditional sequence is inverted: instead of cutting the wafer into chips first and then mounting them, the patent mounts the complete wafer first and then cuts it into individual chips after the redistribution structure is already formed on the carrier board, thus maintaining wafer integrity during the critical mounting phase
Data Source
AI summary
Provided in the present invention is a panel-level packaging method, comprising: providing a plurality of wafers, a hollowed-out panel and a first carrier panel, the hollowed-out panel being provided with a plurality of hollowed-out positions, the size of the hollowed-out positions being slightly larger than that of the wafers, the hollowed-out panel being surface-mounted onto the first carrier panel, front faces of the wafers being provided with a plurality of first welding pads, and the wafers being aimed at the hollowed-out positions and being surface-mounted onto the first carrier panel; forming a first encapsulation layer which at least covers side faces of the wafers; removing the first carrier panel to obtain a first encapsulation structure, and surface-mounting the first encapsulation structure onto a second carrier panel; forming an electrically conductive structure to obtain a semiconductor intermediate structure; and cutting the semiconductor intermediate structure to obtain a plurality of sub-structures.