Parallel Transistor Biasing for Stable Gain-Switched Power Amplifiers

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Solution Overview

Problem

Existing power amplification modules face challenges in suppressing changes in input impedance when gain is adjusted, leading to degraded voltage standing wave ratio (VSWR) due to the need for complex control circuits and changes in the number of operating transistors.

Innovation Solution

A power amplification module configuration that includes transistors connected in parallel with bias resistors, where bias currents are supplied to the transistors' bases through resistors to manage impedance changes across high and low gain modes, ensuring that transistors are not completely switched off in low gain mode to maintain stable impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of operating transistors is changed to adjust the gain, then the gain can be switched in accordance with the output level, but the input impedance of the power amplification circuit changes and the voltage standing wave ratio (VSWR) is degraded

Engineering Contradiction:
Improvegain switching capabilityVSAvoidinput impedance stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The bias current supplied to the first transistor is dynamically adjusted based on the operating mode (high gain or low gain). In high gain mode, a first bias current is supplied, while in low gain mode, a second bias current different from the first is supplied. This dynamic adjustment of bias current compensates for impedance changes caused by transistor switching, thereby maintaining more stable input impedance across different gain settings.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the bias current parameter supplied to the first transistor depending on the gain mode. By supplying different bias currents (first bias current in high gain mode, second bias current in low gain mode), the operating point of the transistor is adjusted to compensate for the impedance changes that would otherwise occur due to the changing number of active transistors, thus maintaining input impedance stability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a complicated large-scale control circuit is mounted to suppress variations in input impedance, then the input impedance variations can be suppressed, but the chip area becomes larger

Engineering Contradiction:
Improveinput impedance stabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts the impedance stabilization function from a separate complex control circuit and integrates it into the bias circuit that already exists for transistor control. By adding only necessary bias current supply components to the existing bias circuit structure, the patent achieves input impedance stabilization without requiring a separate large-scale control circuit, thus minimizing chip area increase.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The impedance stabilization function is merged with the existing bias circuit for the power amplification transistors. The bias circuit is enhanced to supply different bias currents to the first transistor depending on the gain mode, combining the biasing function with the impedance stabilization function in a single integrated circuit block, thereby avoiding the need for separate control circuitry and reducing chip area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10985712B2Power amplification module
Publication Date: 2021.04.20 MURATA MFG CO LTD
  • US10985712B2 patent drawing
  • US10985712B2 patent drawing
  • US10985712B2 patent drawing

AI summary

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.