Parallel Bus Data Encoding for Power Supply Noise Reduction
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Solution Overview
Problem
As interfaces in computing platforms and integrated circuits increase in transmission speed and bus width, power supply variations and noise become significant issues due to large changes in the ratio of '0' bits to '1' bits on parallel data buses, affecting signal integrity and error detection/correction.
Innovation Solution
Encoding data using codes with approximately equal numbers of '0' and '1' bits to stabilize the power supply demands and reduce noise, implemented in both transmitting and receiving devices within the computing platform, which helps in reducing power supply variations and noise, and aids in error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transmission speed and bus width are increased, then data transmission performance is improved, but power supply variations and noise increase
Solution Approach 1:
The patent changes the parameter of bit composition in encoded data from arbitrary ratios to approximately equal numbers of 0s and 1s. This parameter change stabilizes power supply demands during data transmission, reducing power supply variations and noise while maintaining high transmission speed and bus width performance
2Adaptability or versatility
If the ratio of 0 bits to 1 bits varies significantly on the bus, then encoding flexibility is maintained, but power supply noise increases
Solution Approach 1:
The patent applies parameter changes by constraining the bit composition ratio to approximately equal 0s and 1s in encoded data. This constraint reduces power supply noise while preserving encoding flexibility through the use of multiple valid code representations and encoding schemes that satisfy the balanced bit composition requirement
Data Source
AI summary
Embodiments for binary encoding and/or decoding data are disclosed. In one or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein said one of the plurality of codes is selected to most closely maintain a programmable non-equal ratio of bits at a first logical level to bits at a second logical level.