Defect Repair Circuit With Parallel Matching Signal Transmission
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Solution Overview
Problem
Existing memory systems face challenges in efficiently transmitting matching signals to replace defective memory cells with redundant cells, leading to increased transmission delay and reduced repair speed.
Innovation Solution
A defect repair circuit with a matching module and transmission processing module that includes multiple submodules and signal buses, allowing for parallel processing and direct transmission of matching signals without intermediate delays, thereby reducing the burden on internal bus resources and improving transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the matching signal is transmitted through the existing bus structure, then the memory can perform defect repair, but the transmission delay increases and repair speed decreases
Solution Approach 1:
The patent segments the matching signal transmission by introducing dedicated matching signal transmission lines separate from the existing address bus. Each matching submodule has its own direct transmission path to the transmission processing module, avoiding contention and delay on shared bus resources. This segmentation enables parallel transmission of multiple matching signals simultaneously.
Solution Approach 2:
The patent introduces an intermediary transmission processing module that directly receives matching signals from matching submodules through dedicated transmission lines. This intermediary structure acts as a bridge between the matching function and the repair execution function, enabling efficient signal routing without involving the address bus arbitration mechanism.
2Device complexity
If multiple matching signals are transmitted through the same bus, then the circuit structure is simplified, but the bus resource burden increases and transmission efficiency decreases
Solution Approach 1:
The patent divides the transmission path into multiple independent channels, with each matching submodule having a dedicated transmission line. This segmentation eliminates bus contention and allows simultaneous transmission of multiple matching signals, improving transmission efficiency without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent transitions from a single-dimension shared bus architecture to a multi-dimension parallel architecture by introducing separate transmission dimensions for matching signals. This dimensional change allows multiple signals to traverse different physical paths simultaneously, resolving the trade-off between structure simplicity and transmission efficiency.
Data Source
AI summary
A defect repair circuit includes a matching module, a bus, and a transmission processing module. The matching module is connected to the bus and configured to receive a target address and a plurality of defect addresses, match the target address with the plurality of defect addresses respectively to generate a plurality of matching signals, and transmit the matching signals to the bus. The target address is an address to be accessed by the current operation. The transmission processing module is connected to the bus and configured to receive the plurality of matching signals through the bus and generate and output a repair indication signal according to the plurality of matching signals.