Parallel Diode Current Distribution via Parasitic Inductance

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Solution Overview

Problem

Semiconductor elements like IGBTs and diodes connected in parallel exhibit individual differences in manufacturing processes, leading to uneven current distribution, which can concentrate current on certain elements, causing abnormal heat generation and potential breakage.

Innovation Solution

An electronic circuit and semiconductor module design where diodes or switching elements with lower forward or ON voltages are connected in parallel with those having higher voltages, with paths extending via lower voltage elements having larger parasitic inductance to distribute current evenly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple semiconductor elements are connected in parallel to handle heavy current, then the current handling capability is improved, but current concentrates on certain elements due to individual differences, causing abnormal heat generation

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidcurrent distribution uniformity
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies different parasitic inductance values to different current paths by designing wiring members with varying inductance characteristics. Specifically, paths through semiconductor elements with lower forward voltages are assigned larger parasitic inductances, while paths through elements with higher forward voltages are assigned smaller parasitic inductances. This local differentiation compensates for individual element differences and achieves uniform current distribution across all parallel-connected elements.

Inventive Principle:
Principle #3Local quality

2Reliability

If wiring members are designed with different parasitic inductances to suppress current concentration, then current distribution uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvecurrent distribution uniformityVSAvoidwiring member configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parasitic inductance parameter of wiring members to achieve current distribution control. By adjusting the inductance values of different wiring members based on the forward voltage characteristics of connected semiconductor elements, the system achieves uniform current distribution. This parameter-based approach provides a systematic method to balance current flow without requiring complex additional control circuits or active components.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively suppresses current concentration on specific semiconductor elements, preventing abnormal heat generation and enhancing long-term reliability by distributing current across multiple paths.

Implementation Method 1

an inductance of a first path from a first terminal via a first diode to a second terminal is larger than an inductance of a second path from the first terminal via a second diode to the second terminal

Methodology Applied
Scientific EffectParasitic inductance: Inductor

Data Source

PatentUS11631668B2Current concentration-suppressed electronic circuit, and semiconductor module and semiconductor apparatus containing the same
Publication Date: 2023.04.18 FUJI ELECTRIC CO LTD
  • US11631668B2 patent drawing
  • US11631668B2 patent drawing
  • US11631668B2 patent drawing

AI summary

An electronic circuit having a first terminal and a second terminal. The electronic circuit includes a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode that respectively have applied thereto a first forward voltage and a second forward voltage, the second forward voltage being higher than the first forward voltage. A first path and a second path are formed from the first terminal, respectively via the first diode and the second diode, to the second terminal. An inductance of the first path is larger than an inductance of the second path.