Parallel-Fabricated Multilayer PCBs via Conductive Paste Vias
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Solution Overview
Problem
Conventional methods for producing high-density multilayer circuits are sequential, expensive, and prone to defects due to slow and complex plating operations, residual dimples in vias, and mechanical stress issues, which hinder efficient interconnection and component attachment.
Innovation Solution
The method involves aligning and laminating multiple parallel-fabricated circuit layers using a conventional multilayer circuit core, with conductive compound-filled via holes created through a polymer mask and adhesive sheet, allowing for efficient vertical interconnection and eliminating the need for sequential plating and reducing mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential plating operations are used to form via connections, then electrical interconnection between layers is achieved, but the process becomes slow, expensive, and complex
Solution Approach 1:
The patent extracts the plating operation from the via formation process, replacing it with mechanical drilling and filling with conductive material. This removes the slow, complex chemical plating steps while maintaining electrical connectivity, thereby improving productivity without sacrificing connection reliability.
Solution Approach 2:
The patent replaces the chemical-electrochemical plating system with a mechanical drilling and filling system. Instead of using electroless and electrolytic plating baths, the invention uses mechanical means to create via holes and fill them with conductive compound, significantly reducing process complexity and time.
2Reliability
If electroless and electrolytic plating baths are used, then via connections are formed, but the process becomes expensive to install, operate and maintain
Solution Approach 1:
The patent removes the expensive plating bath infrastructure from the manufacturing process. By replacing electroless and electrolytic plating with mechanical drilling and conductive compound filling, the invention eliminates the need for costly chemical baths, reducing installation, operation, and maintenance expenses while maintaining via connection integrity.
Solution Approach 2:
The patent employs disposable drill bits and mechanically removable conductive compound fills instead of expensive, maintainable plating baths. This approach uses simpler, cheaper materials and processes that do not require complex infrastructure, thereby reducing manufacturing costs while achieving the same functional result.
3Reliability
If plated vias are created, then electrical interconnection is achieved, but residual dimples distort overlying circuitry and entrap contaminants
Solution Approach 1:
The patent replaces the plating process that creates dimples with a mechanical drilling and filling process. The drill creates a clean hole without dimples, and the conductive compound fills the hole completely, eliminating the dimple defect that would otherwise distort circuitry and trap contaminants, while maintaining electrical connectivity.
Solution Approach 2:
The patent performs preliminary drilling to create clean via holes before filling them with conductive compound. This preliminary mechanical action ensures that the holes are free of dimples and properly formed, preventing subsequent distortion and contaminant entrapment issues that would arise from plating processes.
4Manufacturing precision
If sequential processing is used, then each layer can be fabricated with precision, but the overall process is slow and defects in late stages cause substantial losses
Solution Approach 1:
The patent segments the manufacturing process into independent parallel operations: multiple layers can be drilled and filled simultaneously rather than sequentially. This segmentation allows each layer to be processed with precision while maintaining high overall productivity, as the operations on different layers do not interfere with each other.
Solution Approach 2:
The patent enables continuous useful action by allowing multiple layers to be processed simultaneously through parallel drilling and filling operations. Instead of waiting for one layer to complete before starting the next, the invention maintains continuous productivity across all layers, reducing total manufacturing time while preserving precision through controlled processes.
Data Source
Figure 1
AI summary
The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.