Parallel FET Relay Timing for Low Resistance and Commutation Stress

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Solution Overview

Problem

Existing solid state relay circuits using multiple field effect transistors in parallel face limitations in reducing overall resistance due to uneven commutation stress distribution, leading to oversized components and potential damage from overheating.

Innovation Solution

A solid state relay circuit design featuring two groups of field effect transistors, where one group handles commutation stress and another with lower resistance is used, with specific gate operations ensuring the commutation FETs are driven on/off before/after the secondary FETs, respectively, to manage stress and reduce overall resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple FETs are connected in parallel to reduce overall resistance, then the resistance decreases, but the commutation stress becomes unevenly distributed causing each FET to be oversized

Engineering Contradiction:

Improveoverall resistanceVSAvoidFET sizing complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The commutation FETs are activated before the secondary FETs during the switching transition, allowing them to handle the commutation stress initially. This preliminary action ensures that when secondary FETs are turned on, the commutation stress has already been managed, enabling smaller FET sizing while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic control of parallel FET groups through separate gate drive circuits. The commutation FETs and secondary FETs are controlled with different timing sequences, allowing the system to adaptively manage current distribution during switching transitions, thereby achieving both low resistance and manageable FET sizes.

Inventive Principle:

Principle #15Dynamics

2Reliability

If FETs are made larger to handle commutation stress, then reliability improves, but the overall resistance reduction benefit is limited

Engineering Contradiction:

Improvecommutation stress handlingVSAvoidoverall resistance

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the parallel FET configuration into two distinct groups: commutation FETs optimized for handling switching stress, and secondary FETs optimized for low resistance conduction. This segmentation allows each group to be sized appropriately for its specific function, achieving both reliability during commutation and low overall resistance during steady state operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different FET groups are designed with different characteristics tailored to their specific roles. Commutation FETs are sized and configured for robust switching performance, while secondary FETs are sized for minimal conduction resistance. This local optimization of quality allows the system to achieve both reliability and low resistance without compromising either aspect.

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If secondary FETs are made smaller to reduce resistance, then overall resistance decreases, but they become vulnerable to damage from commutation stress

Engineering Contradiction:

Improveoverall resistanceVSAvoidoverheating damage

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The commutation FETs are activated in advance before the secondary FETs during switching transitions. This preliminary action ensures that the commutation stress is handled by the robust commutation FETs, protecting the smaller secondary FETs from overheating and damage while still allowing them to contribute to low overall resistance during steady state operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The commutation FETs act as intermediary protective elements that absorb the harmful commutation stress before it can affect the secondary FETs. This intermediary role allows the secondary FETs to be sized smaller for low resistance without being directly exposed to the damaging effects of commutation stress.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves lower overall resistance and protects secondary FETs from damage by optimizing stress distribution, allowing for smaller, more efficient components and improved operational safety.

Implementation Method 1

Field effect transistors (FETs) are transistors in which the voltage at a gate is used to create a field that either facilitates or prevents conduction between a source terminal and a drain terminal

Methodology Applied

Scientific EffectElectric Field: Electric Field

Data Source

PatentUS20150015322A1Parallel FET Solid State Relay Utilizing Commutation FETs

Publication Date: 2015.01.15 ASTRONICS ADVANCED ELECTRONIC SYSTEMS CORP

AI summary

A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.