Parallel FinFET ReRAM Cell Layout for Voltage Support
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Small geometry FinFET transistors in ReRAM memory cells cannot individually support the voltages necessary for programming and erasing, requiring two transistors in series and additional dummy gate lines, which limits area minimization and current handling capabilities.
Innovation Solution
ReRAM memory cells are designed with FinFET transistors in parallel configuration, eliminating the need for dummy gate lines and allowing for simultaneous programming or reading of multiple cells, with bias lines connected globally to rows and bit lines connected to columns, enabling wider metal lines and improved current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two FinFET transistors are placed in series to support programming and erasing voltages, then voltage support capability is improved, but device area increases and current handling capability deteriorates
Solution Approach 1:
The bit line connection is segmented into multiple metal layers (M0, M1, M2) with vertical vias connecting them. This allows the two series transistors to share the voltage stress differently, with each transistor operating within its voltage tolerance while maintaining compact layout.
Solution Approach 2:
The patent transitions from planar transistor layout to three-dimensional FinFET structure with vertical fins extending from the substrate. This vertical dimension increases the effective channel area and current handling capability without increasing the planar footprint, resolving the area constraint while maintaining voltage support.
2Reliability
If two FinFET transistors are placed in series to support programming and erasing voltages, then voltage support capability is improved, but current handling capability deteriorates
Solution Approach 1:
The FinFET structure utilizes vertical fins that extend upward from the substrate, creating multiple parallel conduction paths within a small footprint. This three-dimensional channel structure significantly increases the effective channel width and current handling capability compared to planar transistors, allowing series-connected devices to maintain adequate current drive for programming and erasing operations.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric gate insulators and metal gate electrodes that enable better voltage control and reduced leakage currents. This improves the on-state current capability of each transistor in the series configuration, compensating for the current limitation introduced by series connection.
3Ease of manufacture
If dummy gate lines are added to terminate diffusion regions, then manufacturing compliance is improved, but device complexity and area increase
Solution Approach 1:
The patent removes the need for dummy gate lines by implementing precise diffusion region termination at the edges of active transistor structures. The diffusion regions are designed to naturally terminate at word line boundaries without requiring additional dummy gates, extracting the unnecessary complexity while maintaining manufacturing compliance through careful layout design.
Solution Approach 2:
Instead of adding dummy gate lines to terminate diffusion regions (the conventional approach), the patent inverts the approach by designing diffusion regions that self-terminate at word line boundaries. This reverses the traditional methodology of using dummy structures to achieve compliance, achieving the same manufacturing compliance without the added complexity.
Data Source
AI summary
A ReRAM memory array includes rows and columns of ReRAM cells. Each ReRAM cell in a row and column of the array includes a ReRAM device having an ion source end coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.