Parallel Latch Memory Circuit for Frequency Adaptability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory read operations have a limited operating frequency range due to propagation delays in data paths, leading to data corruption when clock frequencies are reduced, as the assertion of latch signals can occur when incorrect data is available.
Innovation Solution
A memory circuit utilizing multiple parallel latch circuits that update data in a round-robin manner, with a data multiplexer selecting which latch provides output to the data path, allowing for asynchronous operation and maintaining data order across varying frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single latch circuit is used in conventional memory read operations, then the circuit complexity is low, but the operating frequency range is limited and data corruption occurs at lower clock frequencies
Solution Approach 1:
The patent divides the single latch circuit into multiple parallel latch circuits (first latch circuit and second latch circuit). Each latch circuit handles data for specific read operations, allowing the system to operate correctly across a wider frequency range by selecting appropriate latches based on timing requirements.
Solution Approach 2:
The patent introduces a data multiplexer as an intermediary component that selects between multiple latch circuits based on timing conditions. This multiplexer mediates between the parallel latch circuits and the data path, enabling flexible data selection to accommodate varying clock frequencies without data corruption.
2Adaptability or versatility
If the clock frequency is reduced to extend operating frequency range, then adaptability improves, but data corruption occurs due to propagation delays
Solution Approach 1:
The patent uses parallel latch circuits to preliminarily store data at different timing points before it propagates through the data path. By having data ready in multiple latches simultaneously, the system can select the correct data regardless of when the latch signal is asserted, preventing data corruption at lower frequencies.
Solution Approach 2:
The patent implements a selection mechanism that uses timing information as feedback to determine which latch circuit's data should be selected. The data multiplexer responds to timing conditions by selecting appropriate data from the parallel latches, ensuring data integrity across varying frequencies.
3Adaptability or versatility
If multiple parallel latch circuits and a data multiplexer are used, then the operating frequency range is extended, but the device complexity increases
Solution Approach 1:
The patent makes the latch circuits and data multiplexer serve multiple functions: they handle both data storage and timing synchronization, and the multiplexer provides both data selection and timing adjustment. This multi-functionality reduces the need for separate dedicated components, managing the complexity increase.
4Speed
If a fixed number of clock pulses is used for data latching, then synchronization is maintained at maximum frequency, but operation fails at lower frequencies
Solution Approach 1:
The patent transitions from a static fixed-clock-pulse approach to a dynamic system where the effective latching timing can vary. By using parallel latches and a multiplexer, the system dynamically adapts to different clock frequencies, maintaining proper synchronization whether operating at maximum frequency or lower frequencies.
Data Source
AI summary
In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.