Parallel Logic Masks for Adder Sum Computation
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Solution Overview
Problem
Existing digital design computations for addition and condition checks on sums are serial, leading to slow performance due to dependency on sum computation completion, particularly in operations like AND/OR checks, increment/decrement of sum bits, and floating-point operations.
Innovation Solution
The introduction of two masks, O Mask and Z Mask, allows for parallel computation of logical operations, increment, and decrement of sum bits, reducing dependency on sum computation completion by using these masks in place of the sum for AND and OR operations, respectively, with minimal hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial computation is used for addition and condition checks, then hardware complexity is low, but computation speed is slow due to dependency on sum computation completion
Solution Approach 1:
The patent pre-computes mask values (O_mask and Z_mask) from input operands X and Y before the actual sum computation is completed. These masks are generated using simple logic operations (X[k]&Y[k] for O_mask, ~(X[k]|Y[k]) for Z_mask) that can be performed in parallel with the addition process. This preliminary action enables subsequent AND/OR operations to be executed without waiting for the complete sum, thereby improving computation speed while maintaining relatively simple hardware structure.
Solution Approach 2:
The patent introduces mask values (O_mask and Z_mask) as intermediary elements that mediate between the input operands and the final result. Instead of directly computing AND/OR operations on the sum after it's computed, the masks serve as intermediaries that capture the necessary information from the inputs, allowing these operations to proceed in parallel with the addition process. This intermediary approach resolves the speed-complexity contradiction by enabling parallel computation without significantly increasing hardware complexity.
2Productivity
If parallel computation is implemented for AND/OR operations, then computation speed improves, but hardware complexity increases due to additional mask generation circuits
Solution Approach 1:
The patent merges the mask generation logic with the existing adder circuitry. The O_mask generation (X[k]&Y[k]) and Z_mask generation (~(X[k]|Y[k])) are integrated into the same hardware structure that computes the sum, allowing these operations to share resources and execute in parallel without requiring completely separate circuit paths. This merging approach increases operation throughput while minimizing the additional hardware overhead.
Solution Approach 2:
The mask generation circuits serve multiple functions: they generate the masks needed for AND/OR operations, and simultaneously provide information that can be used for other purposes such as carry propagation and sum computation. This multi-functionality allows the same hardware structure to support multiple operations, increasing overall productivity without proportionally increasing hardware complexity.
3Loss of time
If the sum computation is completed before AND/OR operations, then computation accuracy is ensured, but latency increases due to serial dependency
Solution Approach 1:
The patent performs preliminary computation of mask values that capture the essential information needed for AND/OR operations directly from the input operands. Since these masks are derived from X and Y (the inputs to the adder) rather than from the sum itself, they can be computed in parallel with the addition process without introducing errors. This preliminary action reduces latency while ensuring computational correctness by maintaining the proper logical relationships.
Solution Approach 2:
The patent creates copies of the input operands (X and Y) to generate the masks, rather than waiting for the sum to be computed. By working with copies of the original inputs simultaneously, the system can proceed with AND/OR operations without waiting for the addition to complete, thereby reducing latency while maintaining computational accuracy through the use of these parallel copies.
Data Source
AI summary
One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.