Parallel Memory Access Across Sub-Blocks Using Multiple Sense Modules

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Solution Overview

Problem

As memory devices increase in size, the number of wordline tiers and pages per block increases exponentially, leading to longer garbage collection times and deterioration of quality of service metrics due to inefficient memory access operations.

Innovation Solution

Concurrent execution of memory access operations on multiple memory sub-blocks using multiple sense modules, allowing simultaneous read or program operations across subsets of sub-blocks through ganged operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices increase in size with more wordline tiers and pages per block, then storage capacity increases, but garbage collection time increases and quality of service deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidgarbage collection time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The memory block is divided into multiple sub-blocks (first sub-block, second sub-block, etc.), each associated with a dedicated sense module. This segmentation allows independent parallel access to different sub-blocks, enabling simultaneous garbage collection operations on multiple sub-blocks without interference, thus reducing total garbage collection time while maintaining large storage capacity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple sense modules are combined to operate concurrently on different sub-blocks within the same memory block. By merging the capabilities of multiple sense modules and coordinating their operations, the system performs garbage collection across multiple sub-blocks in parallel, achieving faster overall execution compared to sequential single-module operation

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If the number of wordline tiers and pages per block increases, then storage density improves, but memory access operation efficiency deteriorates

Engineering Contradiction:
Improvestorage densityVSAvoidmemory access operation efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The memory block is segmented into multiple sub-blocks with dedicated sense modules, allowing concurrent memory access operations on different sub-blocks. This parallelism maintains high storage density while improving access efficiency by enabling simultaneous read/program operations across multiple sub-blocks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple sense modules operate continuously and concurrently on different sub-blocks, maximizing the utilization of memory resources. While one sense module is accessing data in its associated sub-block, other sense modules simultaneously access their respective sub-blocks, ensuring continuous productive action without idle waiting time

Inventive Principle:
Principle #20Continuity of useful action

3Device complexity

If single sense module is used for memory access operations, then device complexity is low, but operation speed is limited

Engineering Contradiction:
Improvesense module configurationVSAvoidmemory access speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

Multiple sense modules are merged into the memory block structure, each handling a portion of the sub-blocks. This merging of multiple sensing capabilities enables parallel memory access operations, significantly increasing overall access speed while keeping each individual sense module relatively simple in design

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250273275A1Execution of a memory access operation involving multiple memory cells of a memory device using multiple sense modules
Publication Date: 2025.08.28 MICRON TECHNOLOGY INC
  • US20250273275A1 patent drawing
  • US20250273275A1 patent drawing
  • US20250273275A1 patent drawing

AI summary

Control logic in a memory device initiates a memory access operation associated with a memory block of a memory device, wherein the memory block includes a first subset of sub-blocks and a second subset of sub-blocks. During the memory access operation, the control logic causes transmission, via a first sense module coupled to the first subset of sub-blocks, of first data between a page buffer circuit and a first memory cell of the first subset of sub-blocks. During the memory access operation, the control logic causes transmission, via a second sense module coupled to the second subset of sub-blocks, of second data between the page buffer circuit and a second memory cell of the second subset of sub-blocks.