Parallel Memory Operations in Multi-Bonded Semiconductor Dies
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Solution Overview
Problem
Current semiconductor fabrication techniques limit the number of memory cell layers in 3D structures, increasing fabrication costs and compromising areal density and throughput in non-volatile memory devices.
Innovation Solution
An integrated memory module with three semiconductor die, where one die contains control circuitry and two die contain non-volatile memory cells, allowing for increased areal density and throughput without expanding die size, by parallel programming and reading of memory cells across multiple word lines and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell layers in 3D structure is increased to improve areal density, then areal density is improved, but fabrication cost increases dramatically and fabrication reliability deteriorates
Solution Approach 1:
The memory device is divided into multiple semiconductor dies (first die, second die, third die) that are bonded together in a stack. Each die contains a portion of the memory cell layers, allowing the system to achieve high areal density without requiring a single die to contain all layers, thereby reducing fabrication complexity and cost.
Solution Approach 2:
The solution transitions from increasing layers within a single 3D structure to stacking multiple 2D dies vertically. This dimensional approach allows areal density to be improved by adding more dies to the stack rather than increasing the number of layers per die, avoiding the fabrication challenges associated with high-layer-count 3D structures.
2Productivity
If the number of planes of memory cells per die is increased to improve program and read throughput, then program and read throughput is improved, but die size increases which dramatically increases fabrication cost
Solution Approach 1:
Multiple planes of memory cells are distributed across multiple semiconductor dies rather than concentrating all planes in a single die. The control circuitry on one die manages memory operations across all dies, enabling high throughput through parallel access to multiple planes while keeping each individual die size manageable.
Solution Approach 2:
The control circuitry on the third die serves multiple functions by managing memory operations across both the first and second dies simultaneously. This multi-functional control approach enables high throughput operations across multiple planes without requiring each die to be large, as the control logic is shared and reused across the stack.
Data Source
AI summary
A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.