Parallel Memory Cell Access Using Staged Word-Line Voltages
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Solution Overview
Problem
Existing memory devices face increased latency and power consumption when accessing multiple memory cells concurrently due to the need for extensive driving of access circuitry.
Innovation Solution
A memory device is configured to apply sequences of voltages to word lines and bit lines to concurrently access multiple memory cells, allowing independent and simultaneous writing of logic states to each cell based on voltage sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential access operations are used on each memory cell, then device complexity is reduced, but latency increases and productivity decreases
Solution Approach 1:
The memory array is segmented into multiple independently accessible regions or banks, allowing simultaneous access to multiple memory cells through parallel read/write operations. This segmentation enables the system to perform multiple operations concurrently without increasing individual cell access complexity.
Solution Approach 2:
The patent introduces a temporal dimension to memory access by implementing pipelined and overlapped operation sequences. Multiple access operations are executed in different time stages simultaneously, transforming sequential time-based access into parallel spacetime-based access, thereby reducing latency without complicating the fundamental access circuitry.
2Device complexity
If sequential access operations are used on each memory cell, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The system performs preliminary actions by pre-charging bit lines and pre-positioning data in buffer circuits before actual read/write operations. This preparation enables faster execution of memory access operations and allows overlapping of preparation and execution phases, thereby increasing throughput without requiring more complex access circuitry.
Solution Approach 2:
The patent implements continuous useful action through pipelined memory access operations where multiple read and write operations are overlapped in time. While one operation is being executed, the next operation is being prepared, ensuring that the access circuitry is continuously productive without idle cycles, thereby increasing overall throughput.
3Loss of time
If parallel access of multiple memory cells is implemented, then latency is reduced and productivity increases, but use of energy increases
Solution Approach 1:
The system applies partial action by selectively activating only the specific memory cells and circuit pathways needed for current operations, rather than energizing the entire memory array. This selective activation enables parallel access to multiple cells while minimizing the number of active components, thereby reducing overall power consumption.
Solution Approach 2:
Different regions of the memory array are assigned different operational states (active, standby, or powered-down) based on local access requirements. This local quality approach allows parallel operations in active regions while keeping other regions in low-power states, optimizing the balance between latency reduction and energy consumption.
4Productivity
If parallel access of multiple memory cells is implemented, then productivity increases, but device complexity increases
Solution Approach 1:
The access circuitry is designed with universal components that can handle multiple read and write operations through the same physical pathways. By making the access circuitry multi-functional and reusable across different operations, the system achieves high throughput without proportionally increasing hardware complexity.
Solution Approach 2:
Multiple access operations are merged into shared circuit pathways and control logic. The patent combines separate read and write operations into integrated operation sequences that use common bit lines, word lines, and control circuits, thereby increasing productivity while avoiding the need for duplicate circuitry for each operation.
Data Source
AI summary
Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.