Parallel Semiconductor Module Layout for Inductance-Balanced Switching
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Solution Overview
Problem
The existing semiconductor modules experience current imbalance due to differences in self-inductance and parasitic inductance between switching elements connected in parallel, leading to unbalanced gate voltages during switching operations.
Innovation Solution
The semiconductor module is designed with a configuration where the self-inductance and mutual inductance of current paths are optimized to ensure equal inductance sums for each switching element, achieved by strategically positioning the main terminals and heat sinks, thereby balancing the gate voltage and current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple switching elements are connected in parallel and driven by one driver, then the current handling capability is improved, but the current imbalance occurs due to differences in self-inductance and parasitic inductance
Solution Approach 1:
The patent applies asymmetry by intentionally designing different current path layouts for each switching element. Specifically, the first current path and second current path are arranged asymmetrically with respect to the first and second switching elements, respectively. This asymmetric arrangement ensures that the sum of self-inductance and mutual inductance is equalized for both switching elements, thereby balancing the gate voltages and currents despite the parallel connection configuration.
2Ease of operation
If main terminals are horizontally arranged along the alignment direction of switching elements, then the connection simplicity is improved, but the self-inductance difference between current paths increases
Solution Approach 1:
The patent applies local quality by optimizing the specific arrangement of current paths and heat sinks in different regions of the module. The first current path is arranged with a first heat sink, and the second current path is arranged with a second heat sink, creating locally optimized current paths. This local optimization ensures that despite the horizontal arrangement of main terminals for connection simplicity, the self-inductance and mutual inductance sums are equalized, achieving uniform inductance characteristics.
3Area of stationary object
If switching elements are disposed side by side, then the module compactness is improved, but the parasitic inductance difference occurs leading to gate voltage imbalance
Solution Approach 1:
The patent applies dimensionality change by considering the three-dimensional arrangement of current paths and heat sinks. The first and second heat sinks are disposed at different positions and orientations, and the current paths are routed through different spatial dimensions. This three-dimensional optimization allows the switching elements to be disposed side by side for compactness while equalizing the sum of self-inductance and mutual inductance, thereby maintaining gate voltage balance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively restricts current imbalance and ensures balanced gate voltages across switching elements during switching operations, enhancing the performance and reliability of the semiconductor module.
Implementation Method 1
a difference occurs in a self-inductance of a current path provided between the second main electrode (for example, the emitter electrode) and the second main terminal (for example, the emitter terminal)
Implementation Method 2
the self-inductance and mutual inductance of current paths are optimized to ensure equal inductance sums for each switching element
Data Source
Figure 1~2
Figure 3~5
Figure 6~7
AI summary
In a semiconductor module (10), multiple switching elements (12, 13, 34) are connected in parallel with each other. A first current path (25, 26) is formed between each of first main electrodes (14b) and a first main terminal (21), and a second current path (27, 28) is formed between each of second main electrodes and a second main terminal (22). When a self-inductance of an arbitrary current path, which is the second current path of any of the switching elements is denoted as Lsn, a mutual inductance of the arbitrary current path and other current paths except for the arbitrary current path is denoted as Mn, and a sum of Lsn and Mn is denoted as Ln, the switching elements and the current paths are disposed in such a manner that Ln of each of the switching elements is equal to each other.