Parallel MTJ MRAM Cell Layout for Two-Bit Storage
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Solution Overview
Problem
Conventional MRAM cells require multiple cells to store multiple bits, leading to increased area consumption and fabrication costs, as they are limited to two memory states per cell.
Innovation Solution
An MRAM cell design featuring a pair of magnetic tunneling junctions (MTJs) connected in parallel with different dimensions, allowing for four memory states and reducing area consumption by using a single transistor to access both MTJs, thereby storing two bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conventional MRAM cells are used to store multiple bits, then data storage capacity is improved, but area consumption increases
Solution Approach 1:
The patent combines multiple magnetic tunneling junctions (MTJs) with different resistance states into a single MRAM cell structure. By integrating first and second MTJs with distinct resistance characteristics, the cell can represent multiple binary states (00, 01, 10, 11) simultaneously, achieving multi-bit storage in one physical location rather than requiring separate cells for each bit.
Solution Approach 2:
The MRAM cell is designed to perform multiple functions within a single structure: it stores multiple bits of data, provides distinct resistance states for different memory conditions, and maintains non-volatile storage capabilities. The first and second MTJs work together to provide both storage and state differentiation functions that would otherwise require separate components.
2Quantity of substance
If multiple conventional MRAM cells are used to store multiple bits, then data storage capacity is improved, but fabrication cost increases
Solution Approach 1:
The patent merges multiple storage functions into a single fabricatable unit. By designing the MRAM cell to contain multiple MTJs that can be manufactured together in one process cycle, the fabrication cost per bit is reduced compared to producing separate cells for each bit of storage.
Solution Approach 2:
The invention utilizes parameter variations within the same cell structure—specifically, MTJs with different resistance states—to encode multiple bits of information. This approach allows the fabrication process to produce cells with varied characteristics (different resistance values) using the same base manufacturing process, reducing the need for additional fabrication steps or variations.
3Device complexity
If conventional MRAM cells are used with two memory states per cell, then device simplicity is maintained, but area efficiency deteriorates
Solution Approach 1:
The MRAM cell is designed to perform multiple storage functions within a single structure. By integrating first and second magnetic tunneling junctions with different resistance states, the cell can represent multiple binary states (00, 01, 10, 11) simultaneously, achieving multi-bit storage in one physical location rather than requiring separate cells for each bit.
Solution Approach 2:
The invention exploits parameter changes in the magnetic tunneling junctions—specifically variations in resistance states—to encode multiple bits of information. The first MTJ provides a first resistance state and the second MTJ provides a second resistance state, allowing the cell to distinguish between different memory conditions through resistance measurements without increasing physical complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved endurance, data retention, and reduced area usage by half compared to conventional MRAMs, with distinct resistance states enabling efficient writing and reading of multiple bits without the need for additional spacing between transistors.
Implementation Method 1
Magnetoresistive random-access memory (MRAM) is one promising candidate for next generation non-volatile memory technology
Data Source
AI summary
An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.