Parallel Configuration of Multi-Die ICs via Interposer Routing
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Solution Overview
Problem
Verifying the functionality of programmable integrated circuits (ICs) with multiple dies is challenging due to inaccessible signal states, especially at high speeds, and traditional methods like probing are inefficient, especially in flip-chip and ball grid array packaging, which can disrupt system timing and consume valuable PCB space.
Innovation Solution
A method and system for configuring and testing multiple programmable ICs in parallel using a master-slave arrangement, where a master IC transmits configuration data to slave ICs via an interposer with through-silicon-vias and routing circuitry, allowing for simultaneous programming and output monitoring through deterministic number sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional probing methods are used to verify signal states in multiple-die ICs, then verification can be performed, but system timing is disrupted and PCB space is consumed
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the master die and slave dies. The interposer contains routing circuitry and TSVs that enable signal transmission without requiring external probes. This mediator allows verification of signal states while maintaining system timing integrity and avoiding PCB space consumption, as the interposer is integrated into the package substrate rather than requiring external probing equipment
2Difficulty of detecting and measuring
If external probing is used for testing multiple-die ICs, then signal states can be accessed, but valuable PCB space is consumed
Solution Approach 1:
The patent moves the testing and verification functions from the external PCB dimension to the internal package dimension by integrating the interposer within the IC package. The interposer provides routing circuitry and TSVs that enable signal access through the package substrate itself, eliminating the need for external PCB probes and freeing up valuable PCB space while maintaining signal state accessibility
3Ease of manufacture
If sequential configuration method is used for multiple programmable ICs, then configuration can be completed, but configuration time is excessive
Solution Approach 1:
The patent segments the configuration process into parallel operations by introducing a master-slave architecture. The master programmable IC receives the configuration data sequence and simultaneously distributes it to multiple slave programmable ICs through the interposer routing circuitry. This segmentation enables parallel configuration of multiple dies, dramatically reducing total configuration time compared to sequential methods
Solution Approach 2:
The patent enables continuous useful action by allowing configuration data to be transmitted and processed simultaneously across multiple dies. The master IC continuously transmits configuration data through the interposer to multiple slave ICs in parallel, maximizing the utilization of configuration resources and eliminating idle time associated with sequential configuration approaches
Data Source
AI summary
In one embodiment, a configuration data sequence is input to a master programmable integrated circuit (IC). In response to control bits in the configuration data sequence, the master programmable IC transmits the configuration data sequence to one or more slave programmable ICs. The master programmable IC and the one or more slave programmable ICs are configured in parallel with configuration bits from the configuration data sequence.