Parallel Optical Transceiver Module Backside Vias
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Solution Overview
Problem
Current parallel optical modules are complex and costly due to multiple packaging levels and limitations in high-speed performance caused by electrical packaging parasitics, as they require wire bonds and additional wiring for optoelectronic devices on gallium arsenide or indium phosphide substrates that are not transparent at 850 nanometers.
Innovation Solution
A silicon-on-insulator wafer with optically transparent oxide layers and backside optical vias is used, allowing flip-chip attachment of optoelectronic devices directly onto a CMOS integrated circuit chip, eliminating wire bonds and enabling efficient optical coupling through the backside, with reactive-ion etching and photolithographic processes simplifying the formation of optical vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple levels of packaging are used for optoelectronic devices on gallium arsenide or indium phosphide substrates, then the devices can be electrically interconnected to driver integrated circuits, but the packaging becomes complex and costly
Solution Approach 1:
The patent merges the optoelectronic devices and driver integrated circuits onto a single semiconductor substrate, eliminating the need for multiple packaging levels and wire bonds. The semiconductor substrate integrates both the optoelectronic devices and the driver circuits, creating a unified structure that reduces packaging complexity while maintaining electrical interconnection reliability.
Solution Approach 2:
The patent extracts and eliminates the intermediate electrical carrier and wire bonds from the packaging structure. By directly integrating the driver integrated circuits onto the semiconductor substrate containing the optoelectronic devices, the patent removes unnecessary intermediate components and simplifies the electrical interconnection path.
2Reliability
If wire bonds and additional wiring are used for electrical interconnection, then optoelectronic devices can be connected to driver integrated circuits, but high-speed performance is limited due to electrical packaging parasitics
Solution Approach 1:
The patent removes wire bonds and intermediate wiring from the electrical interconnection path by directly integrating the driver integrated circuits onto the semiconductor substrate. This elimination of intermediate components reduces electrical packaging parasitics such as inductance and capacitance, thereby improving high-speed performance while maintaining reliable electrical interconnection.
3Reliability
If optoelectronic devices are packaged in side-by-side configuration with multiple packaging levels, then electrical interconnection is achieved, but the manufacturing process becomes costly and complex
Solution Approach 1:
The patent combines the optoelectronic devices and driver integrated circuits onto a single semiconductor substrate, eliminating the need for multiple packaging levels and intermediate carriers. This integration simplifies the manufacturing process by reducing the number of assembly steps, materials required, and quality control checkpoints, thereby lowering manufacturing costs while maintaining electrical interconnection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical interconnection delays, enhances high-speed performance, and simplifies the manufacturing process by eliminating wire bonds, resulting in a more efficient and cost-effective optical transceiver module with improved optical coupling and monitoring capabilities.
Implementation Method 1
an optically transparent oxide layer is disposed on the silicon substrate, and the optically transparent oxide layer is in contact with the optical vias
Implementation Method 2
reactive-ion etching and photolithographic processes simplifying the formation of optical vias
Implementation Method 3
reactive-ion etching and photolithographic processes simplifying the formation of optical vias
Data Source
AI summary
A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.