Parallel Pattern Recognition Processor Synchronization

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Solution Overview

Problem

Pattern recognition tasks in computing are bottlenecked by the increasing volume of data and number of patterns to be identified, leading to synchronization and timing issues in data stream processing.

Innovation Solution

A pattern-recognition processor system that uses parallel finite state machines to evaluate multiple search criteria simultaneously, allowing for high-bandwidth data stream processing without performance degradation, even with a large number of search criteria.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple patterns are searched sequentially in a data stream, then each pattern can be searched thoroughly, but the processing speed decreases and delay increases

Engineering Contradiction:

Improvepattern recognition accuracyVSAvoiddata stream processing speed

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the pattern recognition task into multiple parallel finite state machines, each responsible for searching a specific pattern. This segmentation allows simultaneous processing of multiple patterns without sequential delays, resolving the contradiction between thorough pattern search and processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by implementing multiple finite state machines that operate simultaneously on the same data stream, enabling both thorough pattern recognition and high processing speed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of search criteria increases, then pattern recognition capability improves, but synchronization problems and timing issues arise

Engineering Contradiction:

Improvepattern recognition capabilityVSAvoidsynchronization and timing

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a universal clock signal that serves all finite state machines simultaneously, providing a common timing reference that ensures synchronization across multiple search criteria. This universal timing mechanism maintains reliability while supporting increased pattern recognition capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses a shared output register that collects results from all finite state machines and provides feedback to the system controller, ensuring that results from multiple parallel searches are properly synchronized and timed before being output, thereby maintaining reliability with increased versatility.

Inventive Principle:

Principle #23Feedback

3Productivity

If parallel processing is implemented to increase speed, then data stream processing improves, but synchronization problems occur

Engineering Contradiction:

Improvedata stream processing speedVSAvoiddata flow timing

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent employs periodic clock signals with fixed periods to control the operation of all finite state machines, ensuring that parallel processing occurs in synchronized time intervals. This periodic timing mechanism maintains data flow timing reliability while achieving high processing speed through parallelism.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent merges the timing control of multiple parallel finite state machines into a single unified clock signal system, and combines their outputs into a shared output register. This merging approach ensures that all parallel operations remain synchronized and that results are properly timed before output.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9164945B2Devices, systems, and methods to synchronize parallel processing of a single data stream

Publication Date: 2015.10.20 MICRON TECHNOLOGY INC

AI summary

Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal. In this manner, the plurality of pattern-recognition processors may be enabled concurrently for synchronized processing of the data stream.