Parallel PCB Manufacturing via Conductive Paste Vias
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Solution Overview
Problem
The manufacturing of printed circuit boards faces challenges due to adhesive shrinkage during curing, leading to stress and unreliable interconnections, and the copper plating process is time-consuming and costly, requiring a more efficient method for quick and reliable interconnection.
Innovation Solution
The method involves parallel processing of metal layer carriers with imaging, etching, and lamination to form copper foil pads, applying conductive paste into micro vias, and attaching carriers with a core subassembly using a single lamination process, reducing the number of process steps and eliminating sequential plating, thereby minimizing stress and manufacturing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential lamination and plating processes are used to manufacture printed circuit boards, then reliable interconnections between circuit layers are achieved, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent combines multiple sequential processes (lamination, via formation, plating) into a single parallel processing step where all metal layer carriers are processed simultaneously through imaging, etching, and lamination to form copper foil pads and micro vias, eliminating the need for sequential plating operations while maintaining interconnection reliability
Solution Approach 2:
The patent segments the circuit board into multiple independent metal layer carriers that can be processed in parallel. Each carrier is processed independently through the same sequence of operations (imaging, etching, lamination), allowing simultaneous production of multiple layers without interfering with each other, thus improving manufacturing efficiency
2Strength
If adhesive curing process is used to bond circuit layers, then permanent physical bonding is achieved, but adhesive shrinkage causes stress and unreliable interconnections
Solution Approach 1:
The patent changes the material parameter from traditional adhesive to a specific lamination adhesive with controlled shrinkage properties. This adhesive is applied in a thin layer and cured under controlled conditions to minimize shrinkage stress while maintaining strong bonding between the metal layer carriers and core subassembly
Solution Approach 2:
The patent applies the lamination adhesive and forms the micro vias with conductive paste filling before final assembly. This preliminary preparation ensures that the adhesive is in optimal condition for bonding, and the micro vias are pre-positioned to accommodate any minimal shrinkage that occurs during curing, preventing stress concentration
3Reliability
If through-hole drilling and copper plating are performed sequentially, then electrical interconnections between layers are established, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges the via formation and copper deposition processes into a single step by using conductive paste filling instead of traditional plating. The conductive paste is applied directly to the micro via openings during the lamination process, eliminating the need for separate drilling, plating, and drying operations
Solution Approach 2:
The patent replaces the electrochemical plating process with a mechanical paste filling process. Conductive paste is screen-printed or deposited directly into the micro via openings, eliminating the need for electroplating equipment and complex chemical baths, thus reducing process complexity and manufacturing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a stress-free and reliable electronic interconnection with reduced manufacturing time and cost, improving the efficiency of printed circuit board production by simplifying the process and eliminating costly plating steps.
Implementation Method 1
attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly
Implementation Method 2
filling conductive paste into the at least one micro via
Data Source
AI summary
Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies are provided. In one embodiment, the invention relates to a method of manufacturing a printed circuit board including providing a core subassembly including at least one metal layer, providing a plurality of one-metal layer carriers after parallel processing each of the plurality of one-metal layer carriers, and attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly.