Parallel Power Simulation Segmentation for ICs
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Solution Overview
Problem
Power simulations of complex integrated circuits are time-consuming due to the need to monitor every gate at every clock cycle, making them take several months to complete, even for a million clock cycles.
Innovation Solution
Divide the serial power consumption simulation into multiple time segments and simulate each segment simultaneously using separate simulation benches, aggregating results to reduce overall simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If every gate is monitored at every clock cycle to accurately simulate power consumption, then measurement precision is improved, but duration of action increases significantly
Solution Approach 1:
The simulation time is divided into multiple segments, and multiple simulations are executed in parallel across different segments. This segmentation allows the total simulation duration to be reduced while maintaining comprehensive monitoring of all gates throughout the entire simulation period, thus resolving the contradiction between measurement precision and duration.
2Reliability
If sequential power simulation is performed for a million clock cycles, then reliability is improved, but loss of time increases significantly
Solution Approach 1:
The million clock cycles are divided into multiple segments, and simulations for different segments are executed simultaneously in parallel. This maintains the comprehensive coverage needed for reliable worst-case power consumption identification while significantly reducing the total time required to complete the simulation.
Solution Approach 2:
The simulation is extended from a single time dimension to multiple parallel time dimensions. By executing simulations for different time segments simultaneously across multiple simulation benches, the total simulation time is reduced while maintaining the same level of reliability through comprehensive coverage of all time segments.
3Productivity
If parallel simulation is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The simulation system is segmented into multiple independent simulation benches, each handling a specific time segment. This segmentation enables parallel execution and improves productivity while keeping each individual simulation bench relatively simple in structure.
Solution Approach 2:
Multiple copies of the simulation bench are created to handle different time segments simultaneously. Each copy is a replica of the basic simulation unit, allowing parallel processing without requiring fundamentally complex new hardware or software architectures, thus improving productivity with moderate increase in system complexity.
Data Source
AI summary
One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.